公开(公告)号：US20060281238A1

公开(公告)日：2006-12-14

申请号：US11474431

申请日：2006-06-26

申请人： Christopher Harris ,  Thomas Gehrke ,  T. Weeks ,  Cem Basceri ,  Elif Berkman

发明人： Christopher Harris ,  Thomas Gehrke ,  T. Weeks ,  Cem Basceri ,  Elif Berkman

IPC分类号： H01L21/338

CPC分类号： H01L29/7783 ,  H01L29/2003

摘要： A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the near-surface region of the substrate. The dopant profile of the buffer layer be smoothly graded, or may consist of sub-layers of different dopant concentration, to also provide a highly resistive upper portion of the buffer layer ideal for subsequent device growth. Also, the buffer layer may be doped with carbon, and aluminum may be used to getter the carbon during epitaxial growth.

摘要翻译： 补偿衬底的近表面区域的电阻率的方法包括在衬底上外延生长缓冲层，其中缓冲液生长为具有取决于衬底的电阻率和导电性的掺杂剂浓度，从而消耗残余或 在基板的近表面区域内的过量电荷。 缓冲层的掺杂剂分布平滑地分级，或者可以由不同掺杂剂浓度的子层构成，还提供缓冲层的高度电阻上部，对于随后的器件生长是理想的。 此外，缓冲层可以掺杂碳，并且可以在外延生长期间使用铝来吸收碳。

公开(公告)号：US07144779B2

公开(公告)日：2006-12-05

申请号：US10931924

申请日：2004-09-01

申请人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

发明人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

IPC分类号： H01L21/336

CPC分类号： H01L29/66787 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。 在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。 单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。 第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。 在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。 然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。 考虑了其他方面和实现。

公开(公告)号：US20060258087A1

公开(公告)日：2006-11-16

申请号：US11486524

申请日：2006-07-13

申请人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

发明人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8238

CPC分类号： H01L29/66787 ,  H01L27/10808 ,  H01L27/10876

摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

公开(公告)号：US20060252224A1

公开(公告)日：2006-11-09

申请号：US11480089

申请日：2006-06-30

申请人： Cem Basceri ,  Gurtej Sandhu

发明人： Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.

公开(公告)号：US07132355B2

公开(公告)日：2006-11-07

申请号：US10932129

申请日：2004-09-01

申请人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

发明人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

IPC分类号： H01L21/44

CPC分类号： H01L29/66787 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66742 ,  H01L29/78642

摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

公开(公告)号：US20060213440A1

公开(公告)日：2006-09-28

申请号：US11430328

申请日：2006-05-09

申请人： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

发明人： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

IPC分类号： C23C16/00

CPC分类号： C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

摘要： The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

公开(公告)号：US20060204649A1

公开(公告)日：2006-09-14

申请号：US11418337

申请日：2006-05-04

申请人： Kevin Beaman ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Er-Xuan Ping ,  David Kubista ,  Cem Basceri ,  Lingyi Zheng

发明人： Kevin Beaman ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Er-Xuan Ping ,  David Kubista ,  Cem Basceri ,  Lingyi Zheng

IPC分类号： C23C16/00 ,  C23C16/52

CPC分类号： C23C16/00 ,  C23C16/46

摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

摘要翻译： 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US20060121672A1

公开(公告)日：2006-06-08

申请号：US11006331

申请日：2004-12-06

申请人： Cem Basceri ,  Gurtej Sandhu

发明人： Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.

摘要翻译： 形成多个电容器的方法包括提供包括侧壁的多个电容器电极。 多个电容器电极至少部分地由与侧壁接合的保持结构支撑，保持结构包括透液材料。 电容器电介质材料沉积在电容器电极上，通过保持结构的流体可渗透材料，其有效地将电容器电介质材料沉积在容纳在保持结构下方的侧壁的部分上。 电容器电极材料通过保持结构的流体可透过材料沉积在电容器介电材料上，有效地将电容器电极材料沉积在容纳在保持结构下方的电容器电介质材料的至少一些之上。 还考虑了与制造方法无关的集成电路。

公开(公告)号：US07023043B2

公开(公告)日：2006-04-04

申请号：US10039215

申请日：2002-01-03

申请人： Cem Basceri ,  Howard E. Rhodes ,  Gurtej Sandhu ,  F. Daniel Gealy ,  Thomas M. Graettinger

发明人： Cem Basceri ,  Howard E. Rhodes ,  Gurtej Sandhu ,  F. Daniel Gealy ,  Thomas M. Graettinger

IPC分类号： H01L29/62

CPC分类号： H01L28/65 ,  H01L21/31637 ,  H01L21/31691 ,  H01L23/5222 ,  H01L27/10852 ,  H01L28/56 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.

公开(公告)号：US07009240B1

公开(公告)日：2006-03-07

申请号：US09598355

申请日：2000-06-21

申请人： Cem Basceri ,  Vishnu K. Agarwal ,  Dan Gealy

发明人： Cem Basceri ,  Vishnu K. Agarwal ,  Dan Gealy

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/02183 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/65 ,  H01L28/91

摘要： Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

摘要翻译： 描述了在高温下抑制电介质降解的系统，装置，结构和方法。 讨论了增强型电容器。 增强电容器包括第一电极，包括五氧化二钽的电介质和具有化合物的第二电极。 该化合物包括第一物质和第二物质。 第二电极包括痕量的第一物质。 当电介质的结晶期间第一物质的痕量被氧化时，半导体结构的形态保持稳定。 在一个实施例中，电介质的晶体结构基本上描述了（001）晶格平面。