公开(公告)号：US07714489B2

公开(公告)日：2010-05-11

申请号：US11545490

申请日：2006-10-11

申请人： Kazuyoshi Torii ,  Kazumasa Yoshida ,  Wataru Matsutani

发明人： Kazuyoshi Torii ,  Kazumasa Yoshida ,  Wataru Matsutani

IPC分类号： F02M57/06 ,  H01T13/20

CPC分类号： H01T21/02 ,  H01T13/32

摘要： A spark plug comprising: a center electrode extending in a direction of an axis of said spark plug; a cylindrical insulator which has a shaft hole, and which holds said center electrode in said shaft hole in a state where a tip end of said center electrode is projected from a tip end face of said insulator; a metal shell which holds said insulator; and a ground electrode in which one end is joined to a tip end face of said metal shell, and which extends from said one end toward another end, wherein said ground electrode has an inner side face which faces said center electrode, and an outer side face which is a back face with respect to said inner side face, said outer side face is formed as an arcuately curved face when viewed from a side of said another end in an extending direction of said ground electrode, and a columnar noble metal tip is joined to said inner side face.

摘要翻译： 一种火花塞，包括：沿所述火花塞的轴线方向延伸的中心电极; 圆柱形绝缘体，其具有轴孔，并且在所述中心电极的前端从所述绝缘体的前端面突出的状态下将所述中心电极保持在所述轴孔中; 保持所述绝缘体的金属外壳; 以及接地电极，其一端接合到所述金属壳的前端面，并且从所述一端向另一端延伸，其中所述接地电极具有面向所述中心电极的内侧面，外侧 面是相对于所述内侧面的背面，当从所述另一端的侧面沿着所述接地电极的延伸方向观察时，所述外侧面形成为弧形弯曲面，柱状贵金属电极头为 连接到所述内侧面。

公开(公告)号：US07586554B2

公开(公告)日：2009-09-08

申请号：US11583882

申请日：2006-10-20

申请人： Daisuke Ryuzaki ,  Kazuyoshi Torii ,  Mutsuko Hatano ,  Daisuke Sonoda ,  Toshiki Kaneko

发明人： Daisuke Ryuzaki ,  Kazuyoshi Torii ,  Mutsuko Hatano ,  Daisuke Sonoda ,  Toshiki Kaneko

IPC分类号： G02F1/136

CPC分类号： G02F1/1362 ,  G02F1/133345 ,  G02F2202/02 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/3185 ,  Y10T428/10

摘要： The present invention provides a liquid crystal display device with high image visibility at low power consumption and produced at low cost by using an interlayer dielectric film, which has low dielectric constant, high heat-resistant property, high optical transmissivity, high film thickness and high flattening property produced at low cost. An organic siloxane dielectric film is used as an interlayer dielectric film of the liquid crystal display device. A ratio of nitrogen content to silicon content (Ni content/Si content) in the interlayer dielectric film is controlled to 0.04 or more in the element ratio. The limiting film thickness to suppress and limit the cracking caused by the thickening of the interlayer dielectric film is set to 1.5 μm or more.

摘要翻译： 本发明提供一种低功耗的高图像可见度的液晶显示装置，通过使用具有低介电常数，高耐热性，高透光率，高膜厚和高的层间绝缘膜以低成本生产的液晶显示装置 以低成本生产的扁平性。 使用有机硅氧烷介电膜作为液晶显示装置的层间电介质膜。 层间电介质膜中的氮含量与硅含量（Ni含量/ Si含量）的比例以元素比控制在0.04以上。 抑制和限制由层间电介质膜的增厚引起的裂纹的限制膜厚设定为1.5μm以上。

公开(公告)号：US07268047B2

公开(公告)日：2007-09-11

申请号：US11357072

申请日：2006-02-21

申请人： Tsunetoshi Arikado ,  Takaaki Kawahara ,  Kazuyoshi Torii ,  Hiroshi Kitajima ,  Seiichi Miyazaki

发明人： Tsunetoshi Arikado ,  Takaaki Kawahara ,  Kazuyoshi Torii ,  Hiroshi Kitajima ,  Seiichi Miyazaki

IPC分类号： H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.

摘要翻译： 硅衬底上的栅极绝缘膜包括SiO 2膜和高k膜。 高k膜含有过渡金属，铝，硅和氧。 高k膜中的硅的浓度高于与SiO 2膜的界面附近的过渡金属和铝的浓度以及与栅电极的界面附近的浓度。 此外，优选至少在与SiO 2膜的界面附近或与栅电极的界面附近的硅中的浓度最高，随着距离逐渐减小 从这些界面，并成为高k电影中心部分中最低的。

公开(公告)号：US20070001244A1

公开(公告)日：2007-01-04

申请号：US11516629

申请日：2006-09-07

申请人： Yasuhiro Shimamoto ,  Katsunori Obata ,  Kazuyoshi Torii ,  Masahiko Hiratani

发明人： Yasuhiro Shimamoto ,  Katsunori Obata ,  Kazuyoshi Torii ,  Masahiko Hiratani

IPC分类号： H01L29/94

CPC分类号： H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02323 ,  H01L21/02329 ,  H01L21/02337 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545

摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

摘要翻译： 在具有SiO 2等效厚度为2nm以上的栅极绝缘膜的FET的制造方法中，与现有的SiO 2相比，能够将漏电流抑制到1/100以下， 在Si衬底（多晶硅栅极）和高介电绝缘膜之间的边界处形成0.5nm或更大的SiO 2 SiO 2膜，并且形成 SiO 2膜比后续步骤中的源极 - 漏极活​​化热处理温度高。 因此，可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低导致的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。

公开(公告)号：US07084558B2

公开(公告)日：2006-08-01

申请号：US10465552

申请日：2003-06-20

申请人： Hideki Teramura ,  Tomoaki Kato ,  Kazuyoshi Torii

发明人： Hideki Teramura ,  Tomoaki Kato ,  Kazuyoshi Torii

IPC分类号： H01T13/20 ,  H01T13/22

CPC分类号： H01T13/32 ,  H01T21/02

摘要： A ground-electrode spark portion 32 is formed from a noble metal which contains Pt as a main component, and is joined to a main metal portion of the ground electrode 4 via an alloy layer which has a thickness ranging from 0.5 μm to 100 μm and in which the noble metal that constitutes the ground-electrode spark portion 32 and the metal that constitutes the main metal portion of the ground electrode 4 are alloyed with each other. The ground-electrode spark portion 32 is configured such that a distal end surface 32t facing a spark discharge gap g is smaller in diameter than a bottom surface 32u joined to the ground electrode 4; and the distal end surface 32t is protrusively located beyond the side surface 4s of the ground electrode 4. When the ground-electrode spark portion 32 is viewed in plane from the distal end surface 32t, a portion of the surface of the ground-electrode spark portion 32 is viewed as a peripheral exposed-region surface 32p which is exposed on the side surface 4s of the ground electrode 4 so as to surround the distal end surface 32t.

摘要翻译： 接地电极火花部32由含有Pt作为主要成分的贵金属形成，并且通过厚度为0.5μm〜100μm的合金层与接地电极4的主金属部接合， 其中构成接地电极火花部分32的贵金属和构成接地电极4的主金属部分的金属彼此合金化。 接地电极火花部32构成为，面向火花放电间隙g的前端面32t的直径小于接合于接地电极4的底面32u的直径。 并且远端表面32t突出地位于接地电极4的侧表面4s之外。 当从前端面32t看平面处接地电极火花部32时，接地电极火花部32的一部分表面被看作暴露在侧面的周边露出区域表面32p 接地电极4的表面4s，以围绕远端表面32t。

公开(公告)号：US20060138572A1

公开(公告)日：2006-06-29

申请号：US11357072

申请日：2006-02-21

申请人： Tsunetoshi Arikado ,  Takaaki Kawahara ,  Kazuyoshi Torii ,  Hiroshi Kitajima ,  Seiichi Miyazaki

发明人： Tsunetoshi Arikado ,  Takaaki Kawahara ,  Kazuyoshi Torii ,  Hiroshi Kitajima ,  Seiichi Miyazaki

IPC分类号： H01L21/8238

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.

摘要翻译： 硅衬底上的栅极绝缘膜包括SiO 2膜和高k膜。 高k膜含有过渡金属，铝，硅和氧。 高k膜中的硅的浓度高于与SiO 2膜的界面附近的过渡金属和铝的浓度以及与栅电极的界面附近的浓度。 此外，优选至少在与SiO 2膜的界面附近或与栅电极的界面附近的硅中的浓度最高，随着距离逐渐减小 从这些界面，并成为高k电影中心部分中最低的。

公开(公告)号：US20050014352A1

公开(公告)日：2005-01-20

申请号：US10889100

申请日：2004-07-13

申请人： Kazuyoshi Torii ,  Riichirou Mitsuhashi ,  Atsushi Horiuchi

发明人： Kazuyoshi Torii ,  Riichirou Mitsuhashi ,  Atsushi Horiuchi

IPC分类号： H01L21/00 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/84 ,  H01L21/3205

CPC分类号： H01L21/823462 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3144

摘要： In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.

公开(公告)号：US06396092B1

公开(公告)日：2002-05-28

申请号：US09381396

申请日：1999-09-20

申请人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

发明人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

IPC分类号： H01L2906

CPC分类号： H01L28/55 ,  H01L28/60

摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.

摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。

公开(公告)号：US06380574B1

公开(公告)日：2002-04-30

申请号：US09674392

申请日：2000-10-31

申请人： Kazuyoshi Torii ,  Yasuhiro Shimamoto ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki

发明人： Kazuyoshi Torii ,  Yasuhiro Shimamoto ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki

IPC分类号： H01L2976

CPC分类号： H01L21/7687 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/75

摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.

摘要翻译： 在下电极的底表面和将下电极连接到开关晶体管的一个扩散层的布线之间延伸的扩散防止层是自对准的。 结果，由于通过使用虚拟膜形成孔图案，所以不产生侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞不与电介质直接接触 具有高介电常数的薄膜。 因此，可以获得高度可靠的装置。

公开(公告)号：US06169324A

公开(公告)日：2001-01-02

申请号：US09413754

申请日：1999-10-06

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L2144

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。