公开(公告)号：US06784040B2

公开(公告)日：2004-08-31

申请号：US10382508

申请日：2003-03-07

申请人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

发明人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

摘要翻译： 非易失性半导体存储器件具有沉积在控制栅电极的每个侧表面上的保护绝缘膜，以在形成浮栅电极期间保护控制栅电极，浮置栅极与其中一个侧表面相对 控制栅电极，其间插入有保护绝缘膜，以便电容耦合到控制栅电极，形成在浮置栅电极和半导体衬底之间的隧道绝缘膜，形成在半导体衬底的包含 并且形成在半导体衬底的与漏极区相对的控制栅电极相对的区域中的源极区。

公开(公告)号：US06686622B2

公开(公告)日：2004-02-03

申请号：US10077979

申请日：2002-02-20

申请人： Fumihiko Noro ,  Seiki Ogura

发明人： Fumihiko Noro ,  Seiki Ogura

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.

摘要翻译： 半导体存储器件包括通过第一绝缘膜形成在半导体衬底的第一主表面上的控制栅极电极和覆盖连接半导体衬底的第一主表面的阶梯区域的浮栅电极和位于 通过第二绝缘膜在比第一主表面更低的水平处，并且具有通过第三绝缘膜与控制栅电极的一个侧表面电容耦合的侧表面。 台阶区域具有与第一主表面连接的第一阶梯部分和连接第一阶梯部分和第二主表面的第二阶梯部分。

公开(公告)号：US06670240B2

公开(公告)日：2003-12-30

申请号：US10218210

申请日：2002-08-13

申请人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

发明人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito ,  Kimihiro Satoh

IPC分类号： H01L21336

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

公开(公告)号：US06611461B2

公开(公告)日：2003-08-26

申请号：US10371514

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06477088B2

公开(公告)日：2002-11-05

申请号：US10005932

申请日：2001-12-05

申请人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito

发明人： Seiki Ogura ,  Tomoko Ogura ,  Tomoya Saito

IPC分类号： G11C1604

CPC分类号： G11C16/14 ,  G11C16/0475

摘要： In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

摘要翻译： 在现有技术中，通过对位扩散施加正偏压和向控制栅极施加负偏压来实现双MONOS存储器擦除。 另一个字栅极和衬底端子接地。 但是由于控制栅极通道长度短，是载波逃逸长度的几倍，因此与控制栅极相邻的字门通道的电压可以显着影响擦除特性和速度。 字门上的负电压提高了擦除速度，而字门下的正通道电位降低了擦除速度。 与现有技术的三阱或物理块分离的擦除阻塞相比，通过存储器阵列的有效偏置，字线或甚至单个存储器单元电平擦除可以没有区域损失。 在没有衬底偏置应用的F-N通道擦除附近，还包括通过字线电压的程序干扰保护。

公开(公告)号：US06366500B1

公开(公告)日：2002-04-02

申请号：US09656395

申请日：2000-09-06

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/5612 ,  H01L27/115 ,  H01L27/11524

摘要： An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

公开(公告)号：US6147379A

公开(公告)日：2000-11-14

申请号：US58803

申请日：1998-04-13

申请人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

发明人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885

摘要： The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region. The drain region includes: a low-concentration impurity layer formed in the second surface region and having one end extending toward the step side region; and a high-concentration impurity layer connected to the low-concentration impurity layer and formed in a region distant from the channel region. An impurity concentration of the low-concentration impurity layer is lower than that of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一电平的第一表面区域，低于第一电平的第二电平的第二表面区域和连接第一和第二电极的台阶侧区域的表面 表面区域 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及经由第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一表面区域是形成在第二表面区域上的外延生长层的上表面。 漏极区域包括：形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层; 以及连接到低浓度杂质层并形成在远离沟道区的区域中的高浓度杂质层。 低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US6144081A

公开(公告)日：2000-11-07

申请号：US540961

申请日：1995-10-11

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

IPC分类号： G03F1/08 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66575 ,  H01L21/28123 ,  H01L29/4238 ,  H01L29/7831

摘要： A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

摘要翻译： 通过在第一和第二浅沟槽边缘处具有第一和第二浅沟槽之间的沟道宽度的浅沟槽隔离来隔离减轻沿着FET器件边缘感应的漏电流的场效应晶体管（FET）器件。 栅极延伸穿过第一和第二浅沟槽之间的沟道宽度。 栅极在浅沟槽边缘处具有第一长度，并且具有小于浅沟槽边缘之间的第一长度的第二长度。 第一长度和第二长度相关联，使得浅沟槽边缘处的阈值电压Vt基本上等于浅沟槽边缘之间的Vt。 FET器件的栅极结构使用独特的相移掩模产生，其允许制造具有非常小的沟道长度的亚微米FET器件。

公开(公告)号：US6074914A

公开(公告)日：2000-06-13

申请号：US182777

申请日：1998-10-30

申请人： Seiki Ogura

发明人： Seiki Ogura

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11517 ,  H01L27/11536 ,  H01L27/11541 ,  H01L29/66825

摘要： A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

摘要翻译： 一种用于电可编程只读存储器件的制造方法，其由控制/字门和控制栅极侧壁上的浮栅组成。 独特的材料选择和阻挡掩模序列允许在精细缩放的CMOS工艺环境内简单和安全地制造具有在浮动栅极下方的超短通道的侧壁浮动栅极，其涉及双侧壁间隔物形成，即一次性侧壁 间隔物和最终的多晶硅间隔栅极。

公开(公告)号：US6002611A

公开(公告)日：1999-12-14

申请号：US120361

申请日：1998-07-22

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/00

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628

摘要： In this invention is described a circuit and method for auto programming of a flash memory cell of an EEPROM. A step split gate is used that has low voltage and low current program conditions. This allows a load device to be connected to each bit line, and sets up a voltage divider between the cell being programmed and the load device. The load device limits the programming current and provides programming data to the cell being programmed. The load device is shut off when the bit line voltage is reduced below a predetermined reference, ending programming of the flash memory cell. The source to drain voltage increases as the memory cell is programmed as a result of the voltage divider between the load device and the cell being programmed thus maintaining pinch off. This produces more energy to program the flash cell and with proper design allows the programming efficiency to be relatively constant over the time that elections are injected onto the floating gate of the flash memory cell. This voltage divider effect also provides for more programming cycles because as charge is built up in the oxide in the vicinity of the floating gate the source to drain voltage is increased automatically providing more energy to program the cell.

摘要翻译： 在本发明中描述了一种用于EEPROM的闪存单元的自动编程的电路和方法。 使用具有低电压和低电流程序条件的分步栅。 这允许负载设备连接到每个位线，并且在被编程的单元和负载设备之间设置分压器。 负载设备限制编程电流，并将编程数据提供给正在编程的单元。 当位线电压降低到低于预定参考值时，负载装置关闭，结束闪存单元的编程。 随着存储器单元被编程，由于负载设备和被编程的单元之间的分压器的结果是保持闭合，源极到漏极电压增加。 这产生更多的能量来编程闪存单元，并且通过适当的设计允许编程效率在选择被注入到闪存单元的浮动栅极上时相对恒定。 该分压器效应还提供更多的编程周期，因为在浮置栅极附近的氧化物中形成电荷，源极到漏极电压自动增加，从而为电池编程提供更多的能量。