公开(公告)号：US06737852B2

公开(公告)日：2004-05-18

申请号：US10033188

申请日：2001-10-25

申请人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G01R2302

CPC分类号： G01R31/31725

摘要： A clock skew measuring apparatus for measuring a clock skew between a plurality of clock signals to be measured in a device under test, includes: a clock signal selecting element for receiving clock signals and outputting them by selecting one of the clock signals one by one; and a clock skew estimator for receiving a reference signal input to the device under test and the clock signals to be measured selected by the clock signal selecting element one by one and for obtaining the clock skew between the clock signals to be measured.

摘要翻译： 一种时钟偏差测量装置，用于测量被测器件中要测量的多个时钟信号之间的时钟偏差，包括：时钟信号选择元件，用于接收时钟信号并通过逐个选择一个时钟信号来输出; 以及时钟偏差估计器，用于一个接一个地接收输入到被测器件的参考信号和由时钟信号选择元件选择的要被测量的时钟信号，并用于获得待测时钟信号之间的时钟偏差。

公开(公告)号：US06653663B2

公开(公告)日：2003-11-25

申请号：US09729424

申请日：2000-12-05

申请人： Masahiro Ishida

发明人： Masahiro Ishida

IPC分类号： H01L2715

CPC分类号： H01L33/32 ,  H01L33/16 ,  H01S5/3202 ,  H01S5/32341

摘要： The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.

摘要翻译： 氮化物半导体器件包括：由含有氮化物的III-V族化合物半导体制成的衬底; 以及由在衬底的主表面上形成的包含氮化物的III-V族化合物半导体层制成的功能区域。 基板的主面从{0001}面倾斜13°〜90°的范围内的角度。

公开(公告)号：US06593765B1

公开(公告)日：2003-07-15

申请号：US09663700

申请日：2000-09-15

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Yoshihiro Hashimoto

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Yoshihiro Hashimoto

IPC分类号： G01R3126

CPC分类号： G01R31/31917 ,  G01R31/3004

摘要： A testing apparatus is able to test a semiconductor integrated circuit with high observability. The testing apparatus includes a test pattern inputting means 14 for inputting a test pattern for activating a path under test of a semiconductor integrated circuit 20 to the semiconductor integrated circuit, a transient power supply current measuring means 16 for measuring transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated, and a fault detecting means 34 for judging absence and presence of a fault of the path under test, based on transient power supply current measured by the transient power supply current measuring means.

摘要翻译： 测试装置能够测试具有高可观察性的半导体集成电路。 测试装置包括测试图案输入装置14，用于输入用于激活半导体集成电路20的测试路径的测试图案到半导体集成电路;瞬态电源电流测量装置16，用于测量提供给半导体集成电路20的瞬态电源电流。 半导体集成电路，同时正在激活测试路径;以及故障检测装置34，用于基于由瞬态电源电流测量装置测量的瞬态电源电流来判断被测路径的故障的不存在和存在。

公开(公告)号：US06593159B1

公开(公告)日：2003-07-15

申请号：US09532063

申请日：2000-03-21

申请人： Tadao Hashimoto ,  Osamu Imafuji ,  Masaaki Yuri ,  Masahiro Ishida

发明人： Tadao Hashimoto ,  Osamu Imafuji ,  Masaaki Yuri ,  Masahiro Ishida

IPC分类号： H01L2100

CPC分类号： H01L33/007 ,  B82Y20/00 ,  C30B25/18 ,  H01S5/0207 ,  H01S5/021 ,  H01S5/2231 ,  H01S5/3201 ,  H01S5/34333 ,  H01S2301/173

摘要： A sapphire substrate, a buffer layer of undoped GaN and a compound semiconductor crystal layer successively formed on the sapphire substrate together form a substrate of a light emitting diode. A first cladding layer of n-type GaN, an active layer of undoped In0.2Ga0.8N and a second cladding layer successively formed on the compound semiconductor crystal layer together form a device structure of the light emitting diode. On the second cladding layer, a p-type electrode is formed, and on the first cladding layer, an n-type electrode is formed. In a part of the sapphire substrate opposing the p-type electrode, a recess having a trapezoidal section is formed, so that the thickness of an upper portion of the sapphire substrate above the recess can be substantially equal to or smaller than the thickness of the compound semiconductor crystal layer.

摘要翻译： 蓝宝石衬底，未掺杂GaN的缓冲层和连续形成在蓝宝石衬底上的化合物半导体晶体层一起形成发光二极管的衬底。 n型GaN的第一包层，未掺杂的In 0.2 Ga 0.8 N的有源层和连续形成在化合物半导体晶体层上的第二覆层一起形成发光二极管的器件结构。 在第二包层上形成p型电极，在第一包层上形成n型电极。 在与p型电极相对的蓝宝石衬底的一部分中，形成具有梯形截面的凹部，使得凹部上方的蓝宝石衬底的上部的厚度可以基本上等于或小于 化合物半导体晶体层。

公开(公告)号：US06589857B2

公开(公告)日：2003-07-08

申请号：US10100118

申请日：2002-03-19

申请人： Masahiro Ogawa ,  Daisuke Ueda ,  Masahiro Ishida

发明人： Masahiro Ogawa ,  Daisuke Ueda ,  Masahiro Ishida

IPC分类号： H01L2120

CPC分类号： C30B33/00 ,  C30B29/403 ,  C30B29/406 ,  C30B29/60 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/0079 ,  H01S5/32341 ,  H01S2304/12

摘要： A first semiconductor film made of a nitride semiconductor is grown through epitaxial growth on a light transmitting substrate. A thermal decomposition layer is disposed in a space between the substrate and the first semiconductor film by irradiating laser light to the first semiconductor film from the back surface of the substrate. After a second semiconductor film made of a nitride semiconductor is grown through epitaxial growth while the first semiconductor film is placed on the substrate, the temperature of the substrate is lowered to room temperature. Then, by separating and removing the substrate from the first and second semiconductor films, it is possible to obtain a nitride semiconductor substrate having an area substantially as large as the area of the substrate.

公开(公告)号：US06566231B2

公开(公告)日：2003-05-20

申请号：US09790908

申请日：2001-02-23

申请人： Masahiro Ogawa ,  Kenji Orita ,  Masahiro Ishida ,  Shinji Nakamura ,  Osamu Imafuji ,  Masaaki Yuri

发明人： Masahiro Ogawa ,  Kenji Orita ,  Masahiro Ishida ,  Shinji Nakamura ,  Osamu Imafuji ,  Masaaki Yuri

IPC分类号： H01L2176

CPC分类号： H01L33/007 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02642 ,  H01L21/02647

摘要： A first semiconductor layer is epitaxially grown on a semiconductor substrate and patterned to form concave and convex portions. A second semiconductor layer is formed on the first semiconductor layer using a top epitaxial mask covering the top surface of the convex portion. Lattice defects D propagating from the first semiconductor layer exist only in a region located above the center of the concave portion (a defect region Ra), while in the other region (a low defect region Rb) lattice defects D propagating from the first semiconductor layer hardly exist.

摘要翻译： 第一半导体层在半导体衬底上外延生长并图案化以形成凹凸部分。 使用覆盖凸部的顶面的顶部外延掩模，在第一半导体层上形成第二半导体层。 从第一半导体层传播的晶格缺陷D仅存在于位于凹部的中心以上的区域（缺陷区域Ra），而在另一区域（低缺陷区域Rb）中，从第一半导体层传播的缺陷D 几乎不存在

公开(公告)号：US06563140B1

公开(公告)日：2003-05-13

申请号：US09392376

申请日：1999-09-09

申请人： Shinji Nakamura ,  Masahiro Ishida ,  Masaaki Yuri ,  Osamu Imafuji ,  Kenji Orita

发明人： Shinji Nakamura ,  Masahiro Ishida ,  Masaaki Yuri ,  Osamu Imafuji ,  Kenji Orita

IPC分类号： H01L3300

CPC分类号： H01S5/2231 ,  H01S5/32341 ,  Y10S438/956

摘要： A semiconductor light emitting device of the present invention includes: a substrate; a light emitting layer; a semiconductor layer of a hexagonal first III-group nitride crystal; and a cladding layer of a second III-group nitride crystal. A stripe groove is provided in the semiconductor layer along a direction.

公开(公告)号：US06562701B2

公开(公告)日：2003-05-13

申请号：US10062512

申请日：2002-02-05

申请人： Masahiro Ishida ,  Daisuke Ueda ,  Masaaki Yuri

发明人： Masahiro Ishida ,  Daisuke Ueda ,  Masaaki Yuri

IPC分类号： H01L21302

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/0079

摘要： A mask film of a material on which substantially no nitride semiconductor grows and having a plurality of openings in a stripe shape is formed on a main surface of a base substrate. Then, on the base substrate, a semiconductor layer of nitride is selectively grown through the mask film. Then, a laser beam is irradiated upon the interface between the semiconductor layer and the base substrate to separate the semiconductor layer from the base substrate, so that a nitride semiconductor substrate is formed from the semiconductor layer.

公开(公告)号：USD467535S1

公开(公告)日：2002-12-24

申请号：US29150336

申请日：2001-11-21

申请人： Masahiro Ishida ,  Hiroyoshi Hibino

设计人： Masahiro Ishida ,  Hiroyoshi Hibino

公开(公告)号：US5655954A

公开(公告)日：1997-08-12

申请号：US564520

申请日：1995-11-29

申请人： Toshio Oishi ,  Shoichi Shin ,  Masafumi Tsunada ,  Masahiro Ishida ,  Yasukazu Mase

发明人： Toshio Oishi ,  Shoichi Shin ,  Masafumi Tsunada ,  Masahiro Ishida ,  Yasukazu Mase

IPC分类号： B08B1/04 ,  B24B37/10 ,  B24B37/34 ,  B24B53/007 ,  B24B53/017 ,  B24B55/06 ,  H01L21/00 ,  B24B7/00 ,  B24B9/00

CPC分类号： B24B37/107 ,  B08B1/04 ,  B24B37/345 ,  B24B53/017 ,  B24B55/06 ,  H01L21/67028

摘要： Provided is a polishing apparatus which comprises a polishing mechanism for polishing a wafer taken out from a cassette, an attaching-detaching device for attaching to and detaching the wafer from the polishing mechanism, a device for cleaning the polished wafer, and a transportation device for transporting the wafer between the cassette, polishing mechanism, attaching-detaching device, and cleaning device. These devices are arranged individually in compartments. A working chamber is divided into a plurality of compartments by means of partitioning devices. A device for polishing a workpiece is set in one of the compartments. The apparatus is also provided with communication devices for internally connecting the adjacent compartments which are divided by the partitioning devices. The apparatus may further comprise devices for individually controlling the respective internal pressures of the compartments or a device for generating an air flow in the form of a laminar flow in each of the compartments.

摘要翻译： 本发明提供一种研磨装置，其特征在于，包括：研磨从盒取出的晶片的研磨机构，将所述晶片与所述研磨机构连接并从所述研磨机构拆下的安装拆卸装置， 在盒，抛光机构，安装拆卸装置和清洁装置之间传送晶片。 这些设备分别安装在隔间中。 工作室通过分隔装置分成多个隔间。 用于抛光工件的装置设置在隔室中的一个中。 该装置还设置有用于内部连接由分隔装置划分的相邻隔室的通信装置。 该装置还可以包括用于单独控制隔室的相应内部压力的装置或用于在每个隔间中产生层流形式的空气流的装置。