公开(公告)号：US4956681A

公开(公告)日：1990-09-11

申请号：US310463

申请日：1989-02-15

申请人： Naoki Yokoyama ,  Masao Taguchi

发明人： Naoki Yokoyama ,  Masao Taguchi

IPC分类号： H03K19/082 ,  F16L55/00 ,  G11C11/34 ,  G11C11/39 ,  G11C11/56 ,  H01L21/331 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H03K3/29 ,  H03K3/36 ,  H03K19/02 ,  H03K19/14 ,  H03K19/20

CPC分类号： B82Y10/00 ,  F16L55/00 ,  G11C11/39 ,  G11C11/56 ,  H03K3/29 ,  H03K3/36 ,  G11C2211/5614

摘要： A logic gate including a resonant-tunneling transistor and a resistor connected in series thereto. The resonant-tunneling transistor has a superlattice structure. The resonant-tunneling transistor may be a resonant-tunneling hot electron transistor or a resonant-tunneling bipolar transistor. The resonant-tunneling transistor conducts a current between a collector and an emitter. The current has one of at least three different current values in response to a base voltage of one of three different voltage values. The third current value is between the first and second current values, and a second voltage value is between the first and third voltage values. The logic gate outputs one of at least three states, a high state, a low state and a state approximately between the high and low states in response to a signal applied to the logic gate. The signal has an amplitude of one of the first to third voltage values. A logic circuit includes at least three connected resonant-tunneling transistors. The logic circuit maintains at least three states, a high state, a low state, and a state approximately between the high and low states in the respective three resonant-tunneling transistors in response to a pulse signal applied to a base of one of the resonant-tunneling transistors.

摘要翻译： 包括谐振隧穿晶体管和串联连接的电阻器的逻辑门。 谐振隧穿晶体管具有超晶格结构。 谐振隧穿晶体管可以是谐振隧道式热电子晶体管或谐振隧穿双极晶体管。 谐振隧穿晶体管在集电极和发射极之间导通电流。 响应于三个不同电压值之一的基极电压，电流具有至少三个不同电流值中的一个。 第三电流值在第一和第二电流值之间，第二电压值在第一和第三电压值之间。 响应于施加到逻辑门的信号，逻辑门输出至少三个状态中的一个，高状态，低状态和大致在高和低状态之间的状态。 该信号具有第一至第三电压值之一的振幅。 一个逻辑电路包括至少三个连接的谐振隧道晶体管。 逻辑电路响应于施加到谐振隧道晶体管中的一个的基极的脉冲信号，在三个谐振隧穿晶体管中保持至少三个状态，高状态，低状态和大致在高和低态之间的状态 隧道晶体管。

公开(公告)号：US4939568A

公开(公告)日：1990-07-03

申请号：US325122

申请日：1989-03-17

申请人： Takashi Kato ,  Masao Taguchi

发明人： Takashi Kato ,  Masao Taguchi

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0694 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/19041

摘要： The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. In addition, the unit semiconductor ICs have a plurality of conducting posts buried in and penetrating through the substrate and insulated therefrom. The unit semiconductor ICs have interconnection terminals provided on both sides of the substrate for connecting other unit semiconductor ICs or a base plate. By stacking plural unit ICs on the base plate, a very large scale IC can be fabricated. Each constituent IC is formed on a bulk silicon substrate, therefore excellent quality can be obtained. This can be also applied to the fabrication of a ROM structure such as a PROM or MASK ROM, using single unit semiconductor ICs, wherein a wiring for the ROM can be formed on the second surface of the substrate.

摘要翻译： 本发明涉及三维堆叠IC和在基板上形成三维叠层IC的方法。 三维堆叠IC包括单元半导体IC，其具有形成在基板的一个表面上或两个表面上的构成IC。 此外，单元半导体IC具有埋入并穿透基板并与其绝缘的多个导电柱。 单元半导体IC具有设置在基板两侧的互连端子，用于连接其它单元半导体IC或基板。 通过在基板上堆叠多个单元IC，可以制造非常大规模的IC。 每个组成IC形成在体硅衬底上，因​​此可以获得优异的质量。 这也可以应用于使用单个单位半导体IC的诸如PROM或MASK ROM的ROM结构的制造，其中可以在基板的第二表面上形成用于ROM的布线。

公开(公告)号：US4791616A

公开(公告)日：1988-12-13

申请号：US879782

申请日：1986-06-27

申请人： Masao Taguchi ,  Yoshihiro Takemae

发明人： Masao Taguchi ,  Yoshihiro Takemae

IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/409

摘要： A semiconductor memory device comprises a memory cell array constituted by a plurality of pairs of memory groups. Two memory gruops of each pair of memory groups have sense amplifiers respectively driven with mutually opposite phases, so as to cancel noise in the bit lines and stabilize the potential of the cell plate.

摘要翻译： 半导体存储器件包括由多对存储器组构成的存储单元阵列。 每对存储器组的两个存储器块分别具有分别以相反相位驱动的读出放大器，以消除位线中的噪声并稳定电池板的电位。

公开(公告)号：US07692253B2

公开(公告)日：2010-04-06

申请号：US11412574

申请日：2006-04-27

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： H01L27/088

CPC分类号： H01L27/101 ,  H01L27/105

摘要： In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.

公开(公告)号：US20080175035A1

公开(公告)日：2008-07-24

申请号：US11724788

申请日：2007-03-16

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/00 ,  G11C11/56 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/79

摘要： A resistance changing memory unit cell includes a resistance changing memory element coupled to a sense bit line and a diode coupled to the resistance changing memory element.

摘要翻译： 电阻变化存储单元包括耦合到感测位线的电阻变化存储元件和耦合到电阻变化存储元件的二极管。

公开(公告)号：US20080098165A1

公开(公告)日：2008-04-24

申请号：US11974295

申请日：2007-10-11

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

IPC分类号： G06F12/00

CPC分类号： G11C16/26

摘要： A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.

摘要翻译： 一种半导体器件，包括：包括非易失性存储单元的存储单元阵列; 包含在存储单元阵列中并存储区域数据的区域; 第一存储单元，保存从存储单元阵列传送的数据，并输出数据; 以及控制电路，其选择用于使所述第一存储单元保持从所述存储单元阵列传送的区域数据并输出所述区域数据的主读取模式;以及辅助读取模式，用于使所述第一存储单元保持多个 通过划分区域数据并从存储单元阵列传送而形成的分割数据并输出分割数据。

公开(公告)号：US20070268744A1

公开(公告)日：2007-11-22

申请号：US11419705

申请日：2006-05-22

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C16/04

CPC分类号： H01L27/11524 ,  G11C11/4045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/808 ,  H01L29/812

摘要： A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.

摘要翻译： 提供了一种存储系统，其形成具有第一侧和第二侧的开关元件，形成具有栅极端子的单元晶体管，形成具有开关元件和单元晶体管的存储单元，栅极端子连接到第二侧 连接字线和第一侧的存储单元，连接位线和存储单元，以及连接参考源和存储单元。

公开(公告)号：US06720804B2

公开(公告)日：2004-04-13

申请号：US10277986

申请日：2002-10-23

申请人： Masao Taguchi ,  Yoshihiro Takemae

发明人： Masao Taguchi ,  Yoshihiro Takemae

IPC分类号： H03B100

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US06329871B2

公开(公告)日：2001-12-11

申请号：US09741796

申请日：2000-12-22

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G05F110

CPC分类号： G05F3/262 ,  G11C5/147

摘要： A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.

公开(公告)号：US06184737B2

公开(公告)日：2001-02-06

申请号：US08813358

申请日：1997-03-07

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： H03K1716

CPC分类号： H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298

摘要： A signal-transmission system includes signal-transmission lines connected to a terminal voltage via terminal resistances, open-drain-type transistors outputting signals to the signal-transmission lines, branch lines stemming from the signal-transmission lines to connect the open-drain-type transistors with the signal-transmission lines, and insertion resistances inserted in the branch lines in proximity of the signal-transmission lines.

摘要翻译： 信号传输系统包括经由端子电阻连接到端子电压的信号传输线路，向信号传输线路输出信号的开漏型晶体管，源自信号传输线路的分支线路，以连接开漏 - 具有信号传输线的晶体管，以及插入在信号传输线附近的分支线中的插入电阻。