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    Memory access during memory calibration
    61.
    发明授权
    Memory access during memory calibration 有权

    公开(公告)号：US10210102B2

    公开(公告)日：2019-02-19

    申请号：US15485115

    申请日：2017-04-11

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Frederick A. Ware

    IPC: G06F13/16 ,  G06F3/06 ,  G06F12/14 ,  G06F12/02

    Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

    Memory systems and methods for dividing physical memory locations into temporal memory locations
    62.
    发明授权
    Memory systems and methods for dividing physical memory locations into temporal memory locations 有权

    公开(公告)号：US10043560B2

    公开(公告)日：2018-08-07

    申请号：US14194923

    申请日：2014-03-03

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer

    IPC: G11C8/06 ,  G11C8/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/00

    Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

    Memory device with defined programming transaction time
    63.
    发明授权
    Memory device with defined programming transaction time 有权

    公开(公告)号：US09934866B2

    公开(公告)日：2018-04-03

    申请号：US14625505

    申请日：2015-02-18

    Applicant: Rambus Inc.

    Inventor： Brent Haukness ,  Ian Shaeffer

    IPC: G06F12/00 ,  G11C16/32 ,  G11C29/02 ,  G11C29/50 ,  G06F12/02 ,  G11C16/10 ,  G11C16/04 ,  G11C29/44

    CPC classification number: G11C16/32 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/107 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/4402

    Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

    On-Die Termination of Address and Command Signals
    67.
    发明申请
    On-Die Termination of Address and Command Signals 有权

    公开(公告)号：US20170169878A1

    公开(公告)日：2017-06-15

    申请号：US15394009

    申请日：2016-12-29

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Kyung Suk Oh

    IPC: G11C11/4076

    CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

    Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

    Folded memory modules
    69.
    发明授权
    Folded memory modules 有权
    折叠内存模块

    公开(公告)号：US09489323B2

    公开(公告)日：2016-11-08

    申请号：US14182986

    申请日：2014-02-18

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    Abstract translation: 存储器模块包括数据接口，该数据接口包括多个数据线和耦合在数据接口和到一个或多个存储器的数据路径之间的多个可配置开关。 可以通过启用或禁用可配置开关的不同子集来配置内存模块的有效宽度。 可配置开关可以由手动开关，存储器模块上的缓冲器，外部存储器控制器或存储器模块上的存储器来控制。

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