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61.发明授权公开(公告)号：US09774441B2
公开(公告)日：2017-09-26
申请号：US15150355
申请日：2016-05-09
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
CPC classification number: H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the frequency offset, or rate of change of the frequency offset, between an arriving signal and the recovered clock signal.
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62.发明申请公开(公告)号：US20170214515A1
公开(公告)日：2017-07-27
申请号：US15369806
申请日：2016-12-05
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jared L. Zerbe , Carl William Werner
CPC classification number: H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
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63.发明申请Clock and Data Recovery Using Receiver Clock Spread Spectrum Modulation and Offset Compensation 有权使用接收机时钟扩频调制和偏移补偿的时钟和数据恢复公开(公告)号：US20160330013A1
公开(公告)日：2016-11-10
申请号：US15150355
申请日：2016-05-09
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
CPC classification number: H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the frequency offset, or rate of change of the frequency offset, between an arriving signal and the recovered clock signal.
Abstract translation: 一种用于执行时钟和数据恢复的系统和方法。 该系统根据到达信号和恢复的时钟信号之间的频率偏移或频率偏移的变化率的至少三个估计值来设置恢复的时钟信号的相位。
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公开(公告)号：US09419781B2
公开(公告)日：2016-08-16
申请号：US14563626
申请日：2014-12-08
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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65.发明申请公开(公告)号：US20160043861A1
公开(公告)日：2016-02-11
申请号：US14820266
申请日：2015-08-06
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jared L. Zerbe , Carl William Werner
CPC classification number: H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
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Patent Agency Ranking
公开(公告)号：US20150092869A1
公开(公告)日：2015-04-02
申请号：US14507743
申请日：2014-10-06
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
Abstract translation: 一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。
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公开(公告)号：US20150036732A1
公开(公告)日：2015-02-05
申请号：US14462561
申请日：2014-08-19
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
IPC: H04L25/03
CPC classification number: H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.
Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择以确定接收到的数据值。
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公开(公告)号：US20140340120A1
公开(公告)日：2014-11-20
申请号：US14452187
申请日：2014-08-05
Applicant: Rambus Inc.
Inventor： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
IPC: H03D13/00
CPC classification number: H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于同相对准的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。
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公开(公告)号：US08855217B2
公开(公告)日：2014-10-07
申请号：US13633076
申请日：2012-10-01
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
Abstract translation: 一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。
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70.发明申请Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 有权具有时钟恢复电路和自适应采样和均衡器时序的接收器公开(公告)号：US20140169438A1
公开(公告)日：2014-06-19
申请号：US14014047
申请日：2013-08-29
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。
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