公开(公告)号：US11244893B2

公开(公告)日：2022-02-08

申请号：US16033109

申请日：2018-07-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US11003615B2

公开(公告)日：2021-05-11

申请号：US15423479

申请日：2017-02-02

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Gilles Bas ,  Hervé Chalopin ,  François Tailliet

IPC: G06F13/42 ,  G06F1/3212 ,  G06F1/3287 ,  G06F13/364

Abstract: A method to transmit data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.

公开(公告)号：US10559575B2

公开(公告)日：2020-02-11

申请号：US16057193

申请日：2018-08-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  H01L27/11526 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11529 ,  G11C5/02 ,  G11C16/10 ,  G11C16/14

Abstract: A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gate selection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.

公开(公告)号：US10403368B2

公开(公告)日：2019-09-03

申请号：US14849257

申请日：2015-09-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C5/02 ,  G11C8/08 ,  G11C8/10 ,  G11C16/14 ,  G11C16/08 ,  G11C8/12 ,  G11C8/14 ,  G11C16/04

Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.

公开(公告)号：US10275173B2

公开(公告)日：2019-04-30

申请号：US15672475

申请日：2017-08-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

公开(公告)号：US10013208B2

公开(公告)日：2018-07-03

申请号：US15055546

申请日：2016-02-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C29/52

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/10 ,  G11C16/3495 ,  G11C29/52

Abstract: According to one mode of implementation it is proposed to automatically accelerate the write operation by deleting on the basis of the values of the data to be written and optionally on the basis of the values of the data present in the memory the erasure step or the programming step, so doing while optionally using a conventional write command. When the memory is equipped with an error-correcting code based on a Hamming code, a property of the latter makes it possible readily to implement this possible acceleration of the cycles of writings within the memory. This property is that according to which when all the bits of the bytes of a digital word grouping together n bytes are equal to zero, the check bits associated with these bytes are also all equal to zero.

公开(公告)号：US20170337007A1

公开(公告)日：2017-11-23

申请号：US15672475

申请日：2017-08-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G11C5/066 ,  G11C7/10 ,  G11C8/12

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

公开(公告)号：US20170294225A1

公开(公告)日：2017-10-12

申请号：US15630614

申请日：2017-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C11/412 ,  H01L29/423 ,  G11C14/00 ,  H01L29/788 ,  H01L23/522 ,  H01L27/11 ,  H01L29/08 ,  H01L29/51

CPC classification number: G11C11/41 ,  G11C11/4125 ,  G11C14/0054 ,  G11C14/0063 ,  G11C16/0416 ,  H01L23/5226 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US09761316B2

公开(公告)日：2017-09-12

申请号：US15141084

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Victorien Brecte

IPC: G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/065 ,  G11C7/067 ,  G11C7/08 ,  G11C16/08 ,  G11C2207/063

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

公开(公告)号：US20170125112A1

公开(公告)日：2017-05-04

申请号：US15183515

申请日：2016-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24

Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.