公开(公告)号：US20210297074A1

公开(公告)日：2021-09-23

申请号：US17207382

申请日：2021-03-19

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Francesco Tomaiuolo ,  Francesco La Rosa

IPC: H03K17/22 ,  H03K17/14

Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

公开(公告)号：US10686046B2

公开(公告)日：2020-06-16

申请号：US16513145

申请日：2019-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US10541270B2

公开(公告)日：2020-01-21

申请号：US16004195

申请日：2018-06-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/12

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US20190371805A1

公开(公告)日：2019-12-05

申请号：US16542511

申请日：2019-08-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11563 ,  H01L27/11536

Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

公开(公告)号：US10128314B2

公开(公告)日：2018-11-13

申请号：US15398228

申请日：2017-01-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L21/8224 ,  H01L21/336 ,  H01L21/337 ,  H01L27/24 ,  H01L29/732 ,  H01L29/66 ,  H01L45/00

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

公开(公告)号：US20180294313A1

公开(公告)日：2018-10-11

申请号：US16004195

申请日：2018-06-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/12

CPC classification number: H01L27/2409 ,  H01L27/1203 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US09984770B2

公开(公告)日：2018-05-29

申请号：US15140997

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  H03M13/29 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/70 ,  G11C29/72 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  H03M13/2906

Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.

公开(公告)号：US09941010B2

公开(公告)日：2018-04-10

申请号：US15365367

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C8/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C8/12 ,  G11C8/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

公开(公告)号：US20180091094A1

公开(公告)日：2018-03-29

申请号：US15436817

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: H03B1/02 ,  H03K3/03 ,  G11C7/06

CPC classification number: H03K3/0315 ,  G05F3/262 ,  G11C7/062 ,  H03K3/011 ,  H03L1/00 ,  H03L5/00 ,  H03L7/0995

Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.

公开(公告)号：US20170302168A1

公开(公告)日：2017-10-19

申请号：US15363631

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Paola Cavaleri

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C16/30

Abstract: A charge pump circuit can be controlled by a control signal that is generated from a first signal coming from and output signal of the charge pump circuit, from a reference signal, and from a clock signal. The generation of the control signal includes a comparison of the reference signal and of the first signal in tempo with a timing signal coming from the clock signal.