Abstract:
Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).
Abstract:
Methods, systems, and computer-readable storage media for a storage device to, upon receiving a command from a computing host, determine whether or not the command includes location information targeting a particular portion of a NVM of the storage device, the location information having been retrieved by the computing host from a shadow map and included with the command. Upon determining that the command includes location information, the command is processed by the storage device using the included location information. Upon determining that the command does not include location information, the storage device determines the particular portion of the NVM targeted by the command based on a map stored in a memory of the storage device before processing the command.
Abstract:
Methods for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.
Abstract:
Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.
Abstract:
Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with reference cells of a plurality of groups of pages of a non-volatile memory (NVM), and predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages. The predicting of values for an optimal read threshold voltage may be based at least on the selected retention drift predictor scheme and the read retention drift history.
Abstract:
A method for using a variable-size flash translation layer. The method includes reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size; converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and reading the compressed data from at least the particular page in the memory based on the address and the number of read units.
Abstract:
A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
Abstract:
Method and apparatus for managing data in a Non-Volatile Memory (NVD). In some embodiments, management information is stored in a buffer memory using a Solid-State Disk (SSD) controller circuit, the management information comprising a map data structure that associates storage addresses of a host device to physical addresses of the NVD. A location in the management information is determined responsive to a selected host storage address and a programmable parameter by arithmetically dividing in accordance with a divisor specified at least in part by the programmable parameter. The location in the management information is used to direct a transfer of user data by the SSD control circuit between the host device and the NVM.
Abstract:
Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.
Abstract:
An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.