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    SEMICONDUCTOR DEVICE
    63.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150294992A1

    公开(公告)日：2015-10-15

    申请号：US14682476

    申请日：2015-04-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/12 ,  H01L27/088 ,  H01L29/786

    CPC classification number: H01L27/088 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/7869

    Abstract: A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor provided over the first insulator so as to overlap with the first conductor, a second insulator over the oxide semiconductor, a second conductor over the second insulator, and a third conductor and a fourth conductor in contact with the oxide semiconductor. The oxide semiconductor includes a region overlapping with the first region and not overlapping with the second region, and a region not overlapping with the first conductor and overlapping with the second conductor in a region positioned between the third conductor and the fourth conductor when viewed from above. The second transistor is a p-channel transistor. A layer in which the first transistor is provided and a layer in which the second transistor is provided are stacked together.

    Abstract translation: 提供了减小面积的半导体。 第一晶体管包括第一导体，第一导体上的第一绝缘体，设置在第一绝缘体上以与第一导体重叠的氧化物半导体，氧化物半导体上的第二绝缘体，第二绝缘体上的第二导体，以及 与氧化物半导体接触的第三导体和第四导体。 氧化物半导体包括与第一区域重叠并且不与第二区域重叠的区域，以及当从上方观察时，位于第三导体和第四导体之间的区域中与第一导体不重叠并与第二导体重叠的区域 。 第二晶体管是p沟道晶体管。 提供第一晶体管的层和设置第二晶体管的层堆叠在一起。

    SEMICONDUCTOR DEVICE
    64.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150270295A1

    公开(公告)日：2015-09-24

    申请号：US14730436

    申请日：2015-06-04

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    IPC: H01L27/12 ,  H01L27/115 ,  H01L27/11 ,  H01L27/108 ,  H01L29/786 ,  H01L29/24

    CPC classification number: H01L27/1255 ,  G11C16/0433 ,  G11C16/26 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

    Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

    Abstract translation: 本发明的目的是提供一种具有新颖结构的半导体器件，其中在数据存储时间中，即使在不提供电力的情况下也可以存储所存储的数据，并且对写入次数没有限制。 半导体器件包括：第一晶体管，包括第一源极和第一漏极; 使用氧化物半导体材料并且第一源电极和第一漏电极电连接的第一沟道形成区域; 在所述第一通道形成区域上的第一栅极绝缘层; 以及在所述第一栅极绝缘层上方的第一栅电极。 第一晶体管的第一源电极和第一漏电极之一和电容器的一个电极彼此电连接。

    SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    65.
    发明申请
    SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
    半导体器件，电子元件和电子器件

    公开(公告)号：US20150269977A1

    公开(公告)日：2015-09-24

    申请号：US14659914

    申请日：2015-03-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takahiko ISHIZU ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Wataru UESUGI

    IPC: G11C5/14 ,  G11C11/409 ,  G11C11/4074

    CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

    Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

    Abstract translation: 提供一种具有存储单元阵列的半导体器件，其能够根据对存储单元阵列的非访问周期而存在于三个电源门控状态。 存储单元阵列包括多个存储单元，每个存储单元具有SRAM和非易失性存储器部分，其具有在通道区域中具有氧化物半导体的晶体管。 三个电源门控状态包括：执行到存储器单元阵列的电源门控的第一状态; 在存储单元阵列上执行功率门控的第二状态和控制存储单元阵列的外围电路; 以及第三状态，其中除了存储单元阵列和外围电路之外，电源电压供应电路经受电源门控。

    SEMICONDUCTOR DEVICE
    66.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150236049A1

    公开(公告)日：2015-08-20

    申请号：US14703384

    申请日：2015-05-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/12 ,  H01L29/04 ,  H01L29/78 ,  H01L29/16 ,  H01L29/786 ,  H01L29/24

    CPC classification number: H01L27/11551 ,  G11C16/0466 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/7869

    Abstract: An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

    Abstract translation: 目的在于提供具有高集成度的新型结构的半导体装置。 半导体器件包括具有沟道形成区域，与沟道形成区域电连接的源电极和漏电极的半导体层，与沟道形成区域重叠的栅极电极，以及沟道形成区域和沟道形成区域之间的栅极绝缘层 栅电极。 当从平面方向看时，具有沟道形成区域的半导体层的侧表面的一部分和源电极或漏电极的侧表面的一部分基本上对准。

    Semiconductor Device
    67.
    发明申请
    Semiconductor Device 审中-公开
    半导体器件

    公开(公告)号：US20150188311A1

    公开(公告)日：2015-07-02

    申请号：US14642002

    申请日：2015-03-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO ,  Asami TADOKORO

    IPC: H02H9/02

    CPC classification number: H02H9/02 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01Q1/2208 ,  H01Q1/2283 ,  Y10T307/858

    Abstract: Of a wireless communication system, an RF tag which can operate normally even when a communication distance is extremely short, like the case where the RF tag is in contact with a reader/writer, whereby the reliability is improved. The RF tag which communicates data by wireless communication includes a comparison circuit which compares electric power supplied from outside with reference electric power and a protection circuit portion which is operated when the electric power supplied from outside is higher than the reference electric power in the comparison circuit.

    Abstract translation: 在无线通信系统中，即使在通信距离非常短的情况下也能正常工作的RF标签，与RF标签与读写器接触的情况一样，由此提高了可靠性。 通过无线通信进行数据通信的RF标签包括比较电路，其将从外部供给的电力与参考电力进行比较，以及当从外部供电的电力高于比较电路中的基准电力时工作的保护电路部分 。

    Bootstrap Circuit and Semiconductor Device Having Bootstrap Circuit
    68.
    发明申请
    Bootstrap Circuit and Semiconductor Device Having Bootstrap Circuit 有权
    自举电路和具有自举电路的半导体器件

    公开(公告)号：US20150091629A1

    公开(公告)日：2015-04-02

    申请号：US14502209

    申请日：2014-09-30

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takahiko ISHIZU ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tatsuya ONUKI

    IPC: H03K17/06

    CPC classification number: G11C5/145 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/785 ,  H01L29/7869 ,  H01L29/78696

    Abstract: A bootstrap circuit of which the capacitance of a bootstrap capacitor is small and which requires a shorter precharge period is provided. The bootstrap circuit includes transistors M41 and M42, capacitors BSC1 and BSC2, an inverter INV41, and keeper circuits 43 and 44. A signal OSG with a high voltage is generated from an input signal OSG_IN. As the signal OSG_IN is made a high level, a node SWG is made a high level by BSC1. After a signal BSE1 is made a high level and the node SWG is made a low level by the keeper circuit 44, a signal BSE2 is made a high level. By the capacitance coupling of BSC2, a voltage of an output terminal 22 increases.

    Abstract translation: 提供了一种自举电路，其自举电容器的电容小并且需要更短的预充电周期。 自举电路包括晶体管M41和M42，电容器BSC1和BSC2，反相器INV41和保持器电路43和44.从输入信号OSG_IN产生具有高电压的信号OSG。 当信号OSG_IN为高电平时，BSC1使节点SWG成为高电平。 在使信号BSE1成为高电平并且节点SWG被保持电路44为低电平之后，使信号BSE2成为高电平。 通过BSC2的电容耦合，输出端子22的电压增加。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    69.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20150024577A1

    公开(公告)日：2015-01-22

    申请号：US14330481

    申请日：2014-07-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO ,  Yasuhiko TAKEMURA ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Shunpei YAMAZAKI

    IPC: G11C16/04 ,  H01L27/115 ,  G11C16/20

    CPC classification number: G11C16/0466 ,  G11C16/20 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11568

    Abstract: A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.

    Abstract translation: 提供了其中校正阈值的半导体器件的制造方法。 在包括多个晶体管的半导体器件中，每个包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在电荷陷阱层 通过进行热处理，同时保持栅电极的电位高于源电极或漏电极的电位1秒以上。 通过该过程，阈值增加并且Icut减小。 用于向栅电极提供信号的电路和用于向源电极或漏电极提供信号的电路彼此电分离。 该处理在前一电路的电位被设置为高于后一电路的电位的状态下执行。

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