公开(公告)号：US20060194403A1

公开(公告)日：2006-08-31

申请号：US11378719

申请日：2006-03-17

申请人： Tingkai Li ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/20

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1

摘要翻译： 已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。 在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜 组成，其中0.1 _0.78Mn^{4+<​​/SUP>_0.22O2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。 在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。 例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

公开(公告)号：US20060180817A1

公开(公告)日：2006-08-17

申请号：US11061946

申请日：2005-02-17

申请人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

发明人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC分类号： H01L27/15

CPC分类号： H05B33/145

摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

摘要翻译： 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

公开(公告)号：US20060172555A1

公开(公告)日：2006-08-03

申请号：US11049594

申请日：2005-02-01

申请人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： C23C14/5806 ,  C23C14/10

摘要： A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon oxide layer; and annealing the substrate to form nanometer sized silicon particles therein.

摘要翻译： 形成其中具有纳米尺寸硅颗粒的富硅氧化硅层的方法包括制备衬底; 准备一个目标 将基板和靶放置在溅射室中; 设置溅射室参数; 将材料从靶材沉积到衬底上以形成富硅氧化硅层; 并对衬底退火以在其中形成纳米尺寸的硅颗粒。

公开(公告)号：US20060088974A1

公开(公告)日：2006-04-27

申请号：US10971387

申请日：2004-10-21

申请人： Wei-Wei Zhuang ,  David Evans ,  Fengyan Zhang ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  David Evans ,  Fengyan Zhang ,  Sheng Hsu

IPC分类号： H01L21/20 ,  H01L21/00

CPC分类号： H01L45/1608 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1283 ,  C23C18/1295 ,  H01L21/31691 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.

摘要翻译： 制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

公开(公告)号：US20060068099A1

公开(公告)日：2006-03-30

申请号：US10957304

申请日：2004-09-30

申请人： Tingkai Li ,  Lawrence Charneski ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Lawrence Charneski ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

IPC分类号： C23C16/00

CPC分类号： C23C16/40 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： The present invention discloses a method to achieve grading PCMO thin film for use in RRAM memory devices since the contents of Ca, Mn and Pr in a PCMO film can have great influence on its switching property. By choosing precursors for Pr, Ca and Mn having different deposition rate behaviors with respect to deposition temperature or vaporizer temperature, PCMO thin film of grading Pr, Ca or Mn distribution can be achieved by varying that process condition during deposition. The present invention can also be broadly applied to the fabrication of any multicomponent grading thin film process by varying any of the deposition parameters after preparing multiple precursors to have different deposition rate behaviors with respect to that particular process parameter. The present invention starts with a proper selection of precursors in which the selected precursors have different deposition rates with respect to at least one deposition condition such as deposition temperature or vaporizer temperature. The precursors can then be arranged in different delivery systems, or can be pre-mixed in a proper ratio for use in a delivery system, or in any other combinations such as a mixture of two or three liquid precursors using a direct liquid injection and a separate gaseous precursor delivery system for gaseous process gas. Then by varying the appropriate deposition condition, a grading thin film can be achieved.

摘要翻译： 本发明公开了一种用于RRAM存储器件中的PCMO薄膜分级的方法，因为PCMO薄膜中Ca，Mn和Pr的含量对其开关性能有很大的影响。 通过选择相对于沉积温度或蒸发器温度具有不同沉积速率行为的Pr，Ca和Mn的前体，可以通过在沉积期间改变该工艺条件来实现分级Pr，Ca或Mn分布的PCMO薄膜。 本发明还可以广泛地应用于任何多组分分级薄膜工艺的制造，其通过在制备多种前体之后改变任何沉积参数以相对于该特定工艺参数具有不同的沉积速率行为。 本发明开始于适当选择前体，其中所选择的前体相对于至少一个沉积条件例如沉积温度或蒸发器温度具有不同的沉积速率。 然后可将前体布置在不同的递送系统中，或者可以以适当的比例预先混合以用于递送系统，或者以任何其它组合例如使用直接液体注射的两种或三种液体前体的混合物 用于气态工艺气体的单独的气态前体输送系统。 然后通过改变适当的沉积条件，可以实现分级薄膜。

公开(公告)号：US20060040413A1

公开(公告)日：2006-02-23

申请号：US10923381

申请日：2004-08-20

申请人： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

发明人： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L27/1085 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

公开(公告)号：US20050266686A1

公开(公告)日：2005-12-01

申请号：US10855088

申请日：2004-05-27

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David Evans ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David Evans ,  Sheng Hsu

IPC分类号： C23C18/12 ,  C30B23/02 ,  C30B29/24 ,  H01L21/44 ,  H01L45/00

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1241 ,  C23C18/1283 ,  C30B23/02 ,  C30B29/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

摘要翻译： 制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

公开(公告)号：US20050243630A1

公开(公告)日：2005-11-03

申请号：US11174034

申请日：2005-07-01

申请人： Sheng Hsu ,  Fengyan Zhang

发明人： Sheng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  G11C7/00

CPC分类号： H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

摘要翻译： 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

公开(公告)号：US20050151210A1

公开(公告)日：2005-07-14

申请号：US10755419

申请日：2004-01-12

申请人： Tingkai Li ,  Sheng Hsu

发明人： Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/28 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.

摘要翻译： 本发明公开了一种使用电阻氧化膜代替栅极电介质的新型铁电晶体管设计。 通过用电阻氧化膜代替栅极电介质，并且通过优化膜电阻的值，铁电层的底栅电连接到硅衬底，消除了捕获的电荷效应并导致存储保持率的提高 特点 电阻氧化膜优选为其中掺杂有杂质物质的导电氧化物的掺杂导电氧化物。 掺杂的导电氧化物最优选为掺杂物质为氧化铪，氧化锆，氧化镧或氧化铝的In 2 N 3 O 3。

公开(公告)号：US20050124112A1

公开(公告)日：2005-06-09

申请号：US10730726

申请日：2003-12-08

申请人： Sheng Hsu ,  Fengyan Zhang

发明人： Sheng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  H01L21/8242

CPC分类号： H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

摘要翻译： 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。