公开(公告)号：US07755379B2

公开(公告)日：2010-07-13

申请号：US12082059

申请日：2008-04-08

申请人： Sik K Lui ,  Anup Bhalla

发明人： Sik K Lui ,  Anup Bhalla

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/2831 ,  G01R31/327

摘要： This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET. Furthermore, the test circuit further includes a timing and make before break (MBB) circuit for receiving an MOSFET failure signal from the MOSFET failure detection circuit and for controlling the first and second switches for switching off a power supply to the MOSFET device upon a detection of an UIS failure under the UIS test to prevent damages to a probe.

摘要翻译： 本发明公开了一种用于对由栅极驱动器驱动的金属氧化物半导体场效应晶体管（MOSFET）器件执行未钳位电感测试的电路。 该电路包括电流检测电路，用于测量从栅极驱动器输入到MOSFET器件的脉冲宽度增加而增加的未钳位电感测试（UIS）电流，其中提供电流检测电路以在栅极驱动器 达到预定义的UIS电流。 测试电路还包括连接到MOSFET器件的漏极端子的MOSFET故障检测电路，用于测量在UIS测试期间检测MOSFET故障的漏极电压变化。 测试电路还包括用于将MOSFET器件的电源接通/断开的第一开关和连接在MOSFET的漏极和源极端子之间的第二开关。 此外，测试电路还包括用于从MOSFET故障检测电路接收MOSFET故障信号的定时和断开前（MBB）电路，并且用于在检测时控制用于关断到MOSFET器件的电源的第一和第二开关 在统计研究所测试下的统计研究所失败，以防止探针受损。

公开(公告)号：US07659570B2

公开(公告)日：2010-02-09

申请号：US11125506

申请日：2005-05-09

申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

摘要翻译： 本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。 开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。 开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。 源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。 半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。 绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

公开(公告)号：US07453119B2

公开(公告)日：2008-11-18

申请号：US11373024

申请日：2006-03-10

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 至少一个有源电池还包括在沟槽之间开放的沟槽的源极触点，其中沟槽的源极触点通过源极区域开放到主体区域中，用于将源区域电连接到设置在绝缘层顶部的源极金属，其中沟槽底部 沟槽源极接触表面进一步用导电材料覆盖，以用作所述活性电池中的集成肖特基势垒二极管。 屏蔽结构设置在底部并与沟槽栅绝缘，以为沟槽栅极和肖特基二极管提供屏蔽效应。

公开(公告)号：US07443225B2

公开(公告)日：2008-10-28

申请号：US11480041

申请日：2006-06-30

申请人： Sik K Lui ,  Anup Bhalla ,  Sanjay Havanur

发明人： Sik K Lui ,  Anup Bhalla ,  Sanjay Havanur

IPC分类号： H01L35/00

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/7803 ,  H01L29/7804 ,  H03K17/08122 ,  H03K2017/0806

摘要： A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.

公开(公告)号：US07378884B2

公开(公告)日：2008-05-27

申请号：US11804877

申请日：2007-05-21

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H03B1/00

CPC分类号： H01L27/088 ,  H01L27/0629 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2223/6644 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48247 ,  H03K17/165 ,  H01L2924/00

摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

公开(公告)号：US07183616B2

公开(公告)日：2007-02-27

申请号：US10208275

申请日：2002-07-30

申请人： Anup Bhalla ,  Sik K Lui ,  Leeshawn Luo ,  Yueh-Se Ho

发明人： Anup Bhalla ,  Sik K Lui ,  Leeshawn Luo ,  Yueh-Se Ho

IPC分类号： H01L23/62 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119 ,  H01L31/113 ,  H01L23/34 ,  H01L23/50

CPC分类号： H01L24/06 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.

摘要翻译： 本发明公开了一种通过在组件中封装几个并联和分离的MOSFET芯片来配置功率MOSFET封装的方法。 该方法还包括将这些MOSFET芯片中的每一个上的栅极焊盘与低电阻栅极总线连接的步骤。 封装电阻和电感显着降低，开关速度和散热明显提高。

公开(公告)号：US10032584B2

公开(公告)日：2018-07-24

申请号：US14585201

申请日：2014-12-30

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01H49/00 ,  H03K17/687 ,  H03K17/0412 ,  H03K17/0812 ,  H03K17/12

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

公开(公告)号：US09806175B2

公开(公告)日：2017-10-31

申请号：US14629229

申请日：2015-02-23

申请人： Anup Bhalla ,  Daniel Ng. ,  Tiesheng Li ,  Sik K. Lui

发明人： Anup Bhalla ,  Daniel Ng. ,  Tiesheng Li ,  Sik K. Lui

IPC分类号： H01L21/337 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

公开(公告)号：US20150206943A1

公开(公告)日：2015-07-23

申请号：US14162220

申请日：2014-01-23

申请人： Madhur Bobde ,  Sik K. Lui ,  Anup Bhalla

发明人： Madhur Bobde ,  Sik K. Lui ,  Anup Bhalla

IPC分类号： H01L29/40 ,  H01L29/06

CPC分类号： H01L29/407 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中并且具有有源电池区域和边缘终止区域，其中边缘终端区域包括填充有场强拥挤减少填充物的宽沟槽和埋在顶表面下方的掩埋场板 并且横向延伸超过场域拥挤场的顶部以使峰值电场横向移动到有源电池区域。 在一个具体的实施例中，场地拥挤减少填料包括填充在宽沟槽中的氧化硅。

公开(公告)号：US08963240B2

公开(公告)日：2015-02-24

申请号：US13870993

申请日：2013-04-26

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/407 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.

摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 构成活性单元的单元中的至少一个具有与沟槽栅极相邻设置的源极区域，该沟槽栅极电连接到栅极焊盘并围绕电池。 沟槽栅极还具有填充有栅极材料的底部屏蔽电极，栅极材料设置在沟槽栅极下方并与沟槽栅极绝缘。 构成由沟槽围绕的源极接触单元中的至少一个具有用作源极连接沟槽的部分的单元填充有栅极材料，用于电连接底部屏蔽电极和直接设置在源极连接沟槽顶部的源极金属 源连接沟槽。 半导体功率器件还包括设置在半导体功率器件的顶部上的绝缘保护层，其具有在源极区域的顶部上的多个源极开口和设置用于电连接到源极金属的源极连接沟槽和至少提供的栅极开口 用于将栅极焊盘电连接到沟槽栅极。