公开(公告)号：US09324391B2

公开(公告)日：2016-04-26

申请号：US12478270

申请日：2009-06-04

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/02 ,  G11C7/10 ,  G06F13/16

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US09123552B2

公开(公告)日：2015-09-01

申请号：US12750448

申请日：2010-03-30

申请人： Brent Keeth ,  Christopher K. Morzano

发明人： Brent Keeth ,  Christopher K. Morzano

IPC分类号： G06F13/14 ,  H01L25/065 ,  G11C5/02 ,  G06F13/38 ,  H01L23/31 ,  H01L23/48 ,  H01L25/18

CPC分类号： H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

摘要： Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

摘要翻译： 各种实施例包括在接口管芯上形成骰子堆叠的装置，堆叠装置和方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。

公开(公告)号：US08205055B2

公开(公告)日：2012-06-19

申请号：US12820877

申请日：2010-06-22

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC分类号： G06F13/16

CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

公开(公告)号：US08183880B2

公开(公告)日：2012-05-22

申请号：US12773505

申请日：2010-05-04

申请人： Timothy Hollis ,  Brent Keeth

发明人： Timothy Hollis ,  Brent Keeth

IPC分类号： H03K17/16

CPC分类号： H03K19/018528 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

摘要： Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.

摘要翻译： 本发明的实施例提供电子设备，存储器件以及驱动芯片上片上信号的方法。 在一个这样的实施例中，生成与片上信号互补的片上信号和第二信号，并将其提供给差分驱动器的两个输入。 差分驱动器电路的一个输出耦合到封装的外部可访问的输出端子。 另一个输出可能会从芯片中脱离，但在封装内。 通过将输出信号和通过封装的第二互补输出路由，可以减少由输出信号引起的串扰。 通过使用电流转向差动驱动器拓扑，也可以减少同时开关输出噪声。 信号对称性也可以提高，减少符号间干扰。

公开(公告)号：US07835207B2

公开(公告)日：2010-11-16

申请号：US12246882

申请日：2008-10-07

申请人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

发明人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

IPC分类号： G11C7/00 ,  G11C8/00 ,  G06F12/00

CPC分类号： G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

摘要翻译： 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

公开(公告)号：US07757061B2

公开(公告)日：2010-07-13

申请号：US11121868

申请日：2005-05-03

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC分类号： G06F13/36

CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

公开(公告)号：US20090245009A1

公开(公告)日：2009-10-01

申请号：US12381143

申请日：2009-03-06

申请人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Demer ,  Ronald L. Taylor ,  John S. Mullin ,  Raymond J. Beffa ,  Frank F. Ross ,  Larry D. Kinsman

发明人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Demer ,  Ronald L. Taylor ,  John S. Mullin ,  Raymond J. Beffa ,  Frank F. Ross ,  Larry D. Kinsman

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

公开(公告)号：US07492652B2

公开(公告)日：2009-02-17

申请号：US11876477

申请日：2007-10-22

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C7/00

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US20080177943A1

公开(公告)日：2008-07-24

申请号：US12069812

申请日：2008-02-12

申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

公开(公告)号：US07310276B2

公开(公告)日：2007-12-18

申请号：US11595515

申请日：2006-11-08

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.