公开(公告)号：US20240276726A1

公开(公告)日：2024-08-15

申请号：US18632806

申请日：2024-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Feng-Cheng Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

公开(公告)号：US12022643B2

公开(公告)日：2024-06-25

申请号：US17036418

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H10B10/00

CPC classification number: H10B10/12

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US11996467B2

公开(公告)日：2024-05-28

申请号：US18317319

申请日：2023-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66636 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

公开(公告)号：US11985825B2

公开(公告)日：2024-05-14

申请号：US17231523

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Feng-Cheng Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

公开(公告)号：US20240138152A1

公开(公告)日：2024-04-25

申请号：US18401988

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H10B51/30

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US11961912B2

公开(公告)日：2024-04-16

申请号：US17833356

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/785 ,  A61B5/150099 ,  A61B5/150992 ,  G01N1/14 ,  G01N33/4915 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/045 ,  H01L29/7853

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US20240096943A1

公开(公告)日：2024-03-21

申请号：US18520346

申请日：2023-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Hsiao-Chiu Hsu ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

公开(公告)号：US11901408B2

公开(公告)日：2024-02-13

申请号：US17175831

申请日：2021-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yih-Ann Lin ,  Yen-Ming Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/10 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76897 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/10 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

公开(公告)号：US11723210B2

公开(公告)日：2023-08-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US11688794B2

公开(公告)日：2023-06-27

申请号：US17651839

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H01L29/66636 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.