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    Dynamic random access memory device
    61.
    发明授权
    Dynamic random access memory device 失效
    动态随机存取存储器

    公开(公告)号：US4484312A

    公开(公告)日：1984-11-20

    申请号：US392077

    申请日：1982-06-25

    申请人： Tomio Nakano ,  Masao Nakano ,  Yoshihiro Takemae ,  Norihisa Tsuge ,  Tsuyoshi Ohira

    发明人： Tomio Nakano ,  Masao Nakano ,  Yoshihiro Takemae ,  Norihisa Tsuge ,  Tsuyoshi Ohira

    IPC分类号： G11C11/401 ,  G11C11/4099 ,  G11C11/40

    CPC分类号： G11C11/4099

    摘要： A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).

    摘要翻译： 一种动态随机存取存储器件，其包括行和列中的单晶体管，单电容器型存储单元（C00 DIFFERENCE C127,127）和虚设单元（DC20'DIFFERENCE DC2,127'，DC20“DIFFERENCE DC2,127” '，DC20'''DIFFERENCE DC2,127'''）。 虚拟单元的电容器（Cd）通过由复位时钟信号（phi R）计时的一个或多个充电晶体管（QA或QA'）充电到高电源电位（VCC）。 虚拟单元的电容器（Cd）由一个或多个晶体管（QB或QB'）放电到低电源电位（VSS），该晶体管（QB或QB'）由具有低于高电源电位的电位的操作时钟信号（phi WL） 电位（VCC）。

    Semiconductor memory device having flip-flop circuits
    62.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US4291394A

    公开(公告)日：1981-09-22

    申请号：US87389

    申请日：1979-10-22

    申请人： Masao Nakano ,  Tomio Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

    发明人： Masao Nakano ,  Tomio Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

    IPC分类号： G11C11/419 ,  G11C5/06 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/4099 ,  H03K3/356 ,  G11C11/40

    CPC分类号： G11C5/063 ,  G11C11/4096 ,  G11C11/4099

    摘要： A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.

    摘要翻译： 一种具有触发电路的半导体存储器件，其中第一和第二位线连接到作为读出放大器的每个触发器电路，第二位线的电位与第一位线的电位相反， 并且第一和第二数据总线分别与第一和第二位线垂直交叉，第一和第二虚拟线分别与第一和第二数据总线线并排布置，以防止I / O放大器连接到第一和第二数据总线。

    Word driver circuit and a memory circuit using the same
    63.
    发明授权
    Word driver circuit and a memory circuit using the same 失效
    字驱动电路和使用其的存储电路

    公开(公告)号：US5640359A

    公开(公告)日：1997-06-17

    申请号：US686385

    申请日：1996-07-25

    申请人： Takaaki Suzuki ,  Yoshihiro Takemae ,  Masao Nakano

    发明人： Takaaki Suzuki ,  Yoshihiro Takemae ,  Masao Nakano

    IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

    CPC分类号： G11C8/14 ,  G11C8/08

    摘要： The present invention relates to a word driver circuit provided in a memory circuit. The word driver circuit comprises a P channel and an N channel transistor having a gate electrode commonly connected and one source or drain electrode commonly connected. The N channeltransistor has another source or drain electrode connected to a ground. A word line is connected to the commonly connected source or drain electrode of the transistors. A first selection signal, generated by decoding a first group of address signals, whose potential is either a first potential by which the N channel transistor is rendered conductive or a second potential lower than the first power supply is supplied to the gate electrodes. And a second selection signal, generated by decoding a second group of address signals, whose potential is either a third potential of the selected word line or a fourth potential equal or lower than the first power supply is supplied to another source or drain of the P transistor.

    摘要翻译： 本发明涉及一种设在存储器电路中的字驱动器电路。 字驱动器电路包括P沟道和N沟道晶体管，其具有共同连接的栅极电极和通常连接的一个源极或漏极电极。 N沟道晶体管具有连接到地的另一个源极或漏极。 字线连接到晶体管的共同连接的源极或漏极。 通过解码第一组地址信号而产生的第一选择信号被提供给栅极电极，该第一组地址信号的电位是N沟道晶体管导通的第一电位或低于第一电源的第二电位。 并且通过解码第二组地址信号而产生的第二选择信号被提供给P的另一个源或漏极，该第二组地址信号的电位是所选字线的第三电位或等于或低于第一电源的第四电位 晶体管。

    Semiconductor memory device having stacked-capacitor type memory cells
    65.
    发明授权
    Semiconductor memory device having stacked-capacitor type memory cells 失效
    具有堆叠电容器型存储单元的半导体存储器件

    公开(公告)号：US4754313A

    公开(公告)日：1988-06-28

    申请号：US93128

    申请日：1987-09-02

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/401 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/02 ,  H01L29/04 ,  H01L29/78

    CPC分类号： G11C11/404 ,  H01L21/8221 ,  H01L27/10808

    摘要： A semiconductor memory device including: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of the word lines and one of the bit lines and including a transfer transistor and a capacitor. Each of the memory cells has a first insulating layer covering a gate of the transfer transistor. The capacitor in each memory cell includes a second conductive layer which contacts one of source and drain regions of the transfer transistor in the memory cell, through the first insulating layer, and extends over the gate of the transfer transistor, a second insulating layer formed on the first conductive layer, and a second conductive layer extending over the second insulating layer. The semiconductor memory device further includes an additional conductive layer directly connected to the other of the source and drain regions of the transfer transistor in the memory cell, through the first insulating layer covering same, and extending over the gate of the adjoining transfer transistors. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. A method for manufacturing a semiconductor memory device having the above construction.

    摘要翻译： 一种半导体存储器件，包括：衬底; 多个字线; 多个位线; 以及多个存储单元，每个存储单元位于由字线之一和一个位线限定的交点处，并且包括转移晶体管和电容器。 每个存储单元具有覆盖转移晶体管的栅极的第一绝缘层。 每个存储单元中的电容器包括第二导电层，其通过第一绝缘层接触存储单元中的转移晶体管的源区和漏区之一，并延伸在转移晶体管的栅极上，第二绝缘层形成在 第一导电层和在第二绝缘层上延伸的第二导电层。 半导体存储器件还包括通过覆盖其的第一绝缘层直接连接到存储单元中的传输晶体管的源极和漏极区域中的另一个的另外的导电层，并且在相邻的转移晶体管的栅极上延伸。 每个位线通过附加导电层连接到另一个源极和漏极区域。 一种具有上述结构的半导体存储器件的制造方法。

    Semiconductor integrated circuit having function for switching operational mode of internal circuit
    67.
    发明授权
    Semiconductor integrated circuit having function for switching operational mode of internal circuit 失效
    具有切换内部电路工作模式功能的半导体集成电路

    公开(公告)号：US4742486A

    公开(公告)日：1988-05-03

    申请号：US861199

    申请日：1986-05-08

    申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

    发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

    IPC分类号： G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G11C11/34 ,  G11C11/401 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C13/00

    CPC分类号： G01R31/31701 ,  G11C29/46 ,  G06F11/267

    摘要： In a semiconductor integrated circuit comprising an internal circuit, a device for receiving a chip select signal from the outside, a device for receiving an input signal from the outside, and a voltage detecting circuit for detecting whether or not the potential of the input signal is higher than a reference potential; the voltage detecting circuit comprises a first device for differentially comparing the potential of the input signal with the reference potential and generating an output potential in accordance with the results of the comparison, a second device for detecting a predetermined edge of the chip select signal so as to trigger the first device, and a third device for latching the output potential of the first device to the third device when the first device is triggered by the second device, the internal circuit being switched from a first mode to a second mode, or vice versa, in accordance with the output potential of the third device.

    摘要翻译： 在包括内部电路的半导体集成电路中，用于从外部接收芯片选择信号的装置，用于从外部接收输入信号的装置以及检测输入信号的电位是否为 高于参考电位; 所述电压检测电路包括用于将所述输入信号的电位与所述参考电位进行差分比较并根据所述比较结果产生输出电位的第一装置，用于检测所述芯片选择信号的预定边沿的第二装置，以便 触发第一装置，以及第三装置，用于当第一装置被第二装置触发时将第一装置的输出电位锁定到第三装置，内部电路从第一模式切换到第二模式，或者副 反之亦然，根据第三器件的输出电位。

    Semiconductor memory device having a circuit for compensating for discriminating voltage of memory cells
    68.
    发明授权
    Semiconductor memory device having a circuit for compensating for discriminating voltage of memory cells 失效
    具有用于补偿存储单元的鉴别电压的电路的半导体存储器件

    公开(公告)号：US4716549A

    公开(公告)日：1987-12-29

    申请号：US901680

    申请日：1986-08-29

    申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

    发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

    IPC分类号： G11C11/407 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/02 ,  G11C11/24

    CPC分类号： G11C11/4099 ,  G11C11/4094

    摘要： A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

    摘要翻译： 一种半导体存储器件，其能够补偿包括存储单元的存储单元和用于将存储单元耦合到位线的门电路的识别电压的变化。 该装置具有用于在复位状态下将位线对预充电到预定的合成预充电电压的预充电电路。 预充电电路对通过在复位状态下将补偿电压加到预充电电压而获得的所得预充电电压对位线对进行预充电。 补偿电压适于基于由于处于活动状态的栅极电路的寄生电容而由字线与存储电容器的电容耦合而引起的存储单元电压的变化来补偿存储单元识别电压的变化，以及 当假设寄生电容不存在时，预充电电压适于优化存储单元识别电压。