公开(公告)号：US11899062B2

公开(公告)日：2024-02-13

申请号：US17605637

申请日：2019-12-24

Applicant: NEC Space Technologies, Ltd.

Inventor： Hiroki Hihara

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/28 ,  G06F11/16 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01R31/3177 ,  G01R31/28 ,  G01R31/3187 ,  G01R31/31724 ,  G01R31/318519 ,  G06F11/16 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.

公开(公告)号：US20240008277A1

公开(公告)日：2024-01-04

申请号：US18469666

申请日：2023-09-19

Applicant: KIOXIA CORPORATION

Inventor： Takanobu ONO ,  Yusuke DOHMAE

IPC: H10B43/27 ,  H01L21/822 ,  H01L29/423 ,  H01L21/28 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/822 ,  H01L29/42344 ,  H01L29/40117 ,  H10B43/35

Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.

公开(公告)号：US20230343795A1

公开(公告)日：2023-10-26

申请号：US18341718

申请日：2023-06-26

Applicant: ROHM CO., LTD.

Inventor： Naoki MATSUMOTO

IPC: H01L27/12 ,  G01R31/28 ,  H01L21/822

CPC classification number: H01L27/124 ,  G01R31/28 ,  H01L21/822 ,  H01L27/1225

Abstract: A semiconductor device 1a includes: a first external terminal 31 to which a first voltage is to be applied; a second external terminal 32 to which a second voltage is to be applied; a third external terminal 33; first wiring 17 connected to the first external terminal 31; second wiring 18 connected to the second external terminal 32; an internal block circuit 11 connected to the first wiring 17; a first resistor 12 and a transistor 14 serially connected between the first wiring 17 and the second wiring 18; and a second resistor 13 connected between the first wiring 17 and the second wiring 18. The transistor 14 turns on or off based on a test signa fed from the third external terminal 33. This configuration enables product identification using a resistance value, even if a predetermined resistance value cannot be changed.

公开(公告)号：US20230317713A1

公开(公告)日：2023-10-05

申请号：US18316466

申请日：2023-05-12

Applicant: Rohm Co., Ltd.

Inventor： Naoki Takahashi

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/06 ,  H01L27/04 ,  H01L23/34 ,  H01L23/00 ,  H01L27/07 ,  H01L29/06 ,  H02H5/04

CPC classification number: H01L27/0296 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/34 ,  H01L24/06 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0292 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/0711 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/78 ,  H01L29/7813 ,  H02H5/044 ,  B60R16/033

Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

公开(公告)号：US11735599B2

公开(公告)日：2023-08-22

申请号：US16971556

申请日：2019-03-08

Applicant: ROHM CO., LTD.

Inventor： Naoki Matsumoto

IPC: H01L27/12 ,  G01R31/28 ,  H01L21/822

CPC classification number: H01L27/124 ,  G01R31/28 ,  H01L21/822 ,  H01L27/1225

Abstract: A semiconductor device 1a includes: a first external terminal 31 to which a first voltage is to be applied; a second external terminal 32 to which a second voltage is to be applied; a third external terminal 33; first wiring 17 connected to the first external terminal 31; second wiring 18 connected to the second external terminal 32; an internal block circuit 11 connected to the first wiring 17; a first resistor 12 and a transistor 14 serially connected between the first wiring 17 and the second wiring 18; and a second resistor 13 connected between the first wiring 17 and the second wiring 18. The transistor 14 turns on or off based on a test signal fed from the third external terminal 33. This configuration enables product identification using a resistance value, even if a predetermined resistance value cannot be changed.

公开(公告)号：US11699698B2

公开(公告)日：2023-07-11

申请号：US17890614

申请日：2022-08-18

Applicant: Rohm Co., Ltd.

Inventor： Naoki Takahashi

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/06 ,  H01L27/04 ,  H01L23/34 ,  H01L23/00 ,  H01L27/07 ,  H01L29/06 ,  H02H5/04 ,  B60R16/033

CPC classification number: H01L27/0296 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/34 ,  H01L24/06 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0292 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/0711 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/78 ,  H01L29/7813 ,  H02H5/044 ,  B60R16/033 ,  H01L2224/0603 ,  H01L2224/06153

Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

公开(公告)号：US20190214355A1

公开(公告)日：2019-07-11

申请号：US16357436

申请日：2019-03-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroshi NISHIKAWA

IPC: H01L23/66 ,  H04B1/40

CPC classification number: H01L23/66 ,  H01L21/822 ,  H01L25/00 ,  H01L27/04 ,  H01L2223/6644 ,  H01L2223/6661 ,  H04B1/00 ,  H04B1/38 ,  H04B1/40

Abstract: A switch IC includes first, second and third switch units, and an amplifier. The first switch unit and the third switch unit are adjacent to each other. The third switch unit and the amplifier are adjacent to each other. The amplifier and the second switch unit are adjacent to each other. The first, second and third switch units, and the amplifier are disposed on a straight line in an order in which a signal passes through the first switch unit, the second switch unit, the third switch unit, and the amplifier.

公开(公告)号：US20190202845A1

公开(公告)日：2019-07-04

申请号：US15857350

申请日：2017-12-28

Applicant: INTEL CORPORATION

Inventor： Chandramouleeswaran Subramani

IPC: C07F7/18 ,  H01L23/498 ,  H01L23/31 ,  C07F7/08 ,  C23C16/18 ,  H01L21/822

CPC classification number: C07F7/1804 ,  C07F7/081 ,  C23C16/18 ,  H01L21/822 ,  H01L23/3128 ,  H01L23/49811

Abstract: An integrated circuit (IC) package comprising a substrate having a dielectric, a first structure over at least a portion of the dielectric, the first structure comprising a molecular compound having a ligand coordinating moiety and a second structure over at least a portion of the first structure, the second structure comprising a metal, wherein the first structure is chemically bonded to the dielectric.

公开(公告)号：US20190189623A1

公开(公告)日：2019-06-20

申请号：US16285834

申请日：2019-02-26

Applicant: ABLIC Inc.

Inventor： Tomomitsu RISAKI

IPC: H01L27/115 ,  G11C11/34 ,  C23C16/24 ,  G11C16/04 ,  H01L21/822 ,  H01L29/788 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L27/115 ,  C23C16/24 ,  G11C11/34 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/283 ,  H01L21/822 ,  H01L29/788

Abstract: Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.

公开(公告)号：US20190158771A1

公开(公告)日：2019-05-23

申请号：US16253365

申请日：2019-01-22

Applicant: SONY CORPORATION

Inventor： Masaaki BAIRO

IPC: H04N5/378 ,  H01L23/522 ,  H04N9/04 ,  H03M1/08 ,  H01L21/822 ,  H03M1/56 ,  H01L27/04

CPC classification number: H04N5/378 ,  H01L21/822 ,  H01L23/5223 ,  H01L27/04 ,  H03M1/08 ,  H03M1/123 ,  H03M1/56 ,  H04N9/045

Abstract: An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.