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    High capacity memory system with improved command-address and chip-select signaling mode
    781.
    发明授权
    High capacity memory system with improved command-address and chip-select signaling mode 有权

    公开(公告)号：US10223299B2

    公开(公告)日：2019-03-05

    申请号：US15101870

    申请日：2014-12-18

    Applicant: RAMBUS INC.

    Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

    IPC: G06F13/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/42

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of mother-board through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    Maintenance operations in a DRAM
    785.
    发明授权
    Maintenance operations in a DRAM 有权

    公开(公告)号：US10168933B2

    公开(公告)日：2019-01-01

    申请号：US15942260

    申请日：2018-03-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C11/406 ,  G11C7/02 ,  G06Q20/00 ,  G06Q10/00 ,  G06F13/16

    Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

    Optimizing power in a memory device
    787.
    发明授权
    Optimizing power in a memory device 有权

    公开(公告)号：US10133338B2

    公开(公告)日：2018-11-20

    申请号：US15589651

    申请日：2017-05-08

    Applicant: RAMBUS INC.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G11C8/00 ,  G06F1/32 ,  G06F5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22 ,  H03L7/081 ,  G11C7/04

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    Area-efficient, width-adjustable signaling interface
    788.
    发明授权
    Area-efficient, width-adjustable signaling interface 有权

    公开(公告)号：US10102887B2

    公开(公告)日：2018-10-16

    申请号：US15793029

    申请日：2017-10-25

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/00 ,  G11C7/10

    Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

    Memory Controllers, Systems, and Methods Supporting Multiple Request Modes
    789.
    发明申请
    Memory Controllers, Systems, and Methods Supporting Multiple Request Modes 审中-公开

    公开(公告)号：US20180268882A1

    公开(公告)日：2018-09-20

    申请号：US15916193

    申请日：2018-03-08

    Applicant: Rambus Inc.

    Inventor： Richard E. Perego ,  Frederick A. Ware

    IPC: G11C7/10 ,  G11C5/06 ,  G06F13/16

    CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

    STACKED SEMICONDUCTOR DEVICE
    790.
    发明申请
    STACKED SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180211701A1

    公开(公告)日：2018-07-26

    申请号：US15872840

    申请日：2018-01-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/04

    Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

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