公开(公告)号：US07195985B2

公开(公告)日：2007-03-27

申请号：US11029740

申请日：2005-01-04

Applicant: Anand Murthy ,  Glenn A. Glass ,  Andrew N. Westmeyer ,  Michael L. Hattendorf ,  Jeffrey R. Wank

Inventor： Anand Murthy ,  Glenn A. Glass ,  Andrew N. Westmeyer ,  Michael L. Hattendorf ,  Jeffrey R. Wank

IPC: H01L21/331

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7834

Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

公开(公告)号：US20070004123A1

公开(公告)日：2007-01-04

申请号：US11173660

申请日：2005-06-30

Applicant: Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

Inventor： Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

IPC: H01L21/8238

CPC classification number: H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract translation: 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US07129139B2

公开(公告)日：2006-10-31

申请号：US10744195

申请日：2003-12-22

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

IPC: H01L21/8234

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

公开(公告)号：US20060134872A1

公开(公告)日：2006-06-22

申请号：US11014937

申请日：2004-12-17

Applicant: Michael Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew Westmeyer

Inventor： Michael Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew Westmeyer

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

公开(公告)号：US20060046399A1

公开(公告)日：2006-03-02

申请号：US10925566

申请日：2004-08-25

Applicant: Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

Inventor： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

Abstract translation: 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US06974733B2

公开(公告)日：2005-12-13

申请号：US10463080

申请日：2003-06-16

Applicant: Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

Inventor： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/338

CPC classification number: H01L29/7842 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/7827

Abstract: There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.

Abstract translation: 公开了一种装置，包括应变基片，包括通道的衬底上的器件，其中应变衬底沿着基本上垂直于沟道中的电流方向的方向施加器件。

公开(公告)号：US20050253200A1

公开(公告)日：2005-11-17

申请号：US11171097

申请日：2005-06-29

Applicant: Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

IPC: H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US20050136584A1

公开(公告)日：2005-06-23

申请号：US10747321

申请日：2003-12-23

Applicant: Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

Inventor： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

IPC: H01L21/20 ,  H01L21/205 ,  H01L31/0328 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract translation: 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US20050130454A1

公开(公告)日：2005-06-16

申请号：US10731269

申请日：2003-12-08

Applicant: Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

IPC: H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract translation: 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

公开(公告)号：US20050087801A1

公开(公告)日：2005-04-28

申请号：US10692696

申请日：2003-10-24

Applicant: Nick Lindert ,  Anand Murthy ,  Justin Brask

Inventor： Nick Lindert ,  Anand Murthy ,  Justin Brask

IPC: H01L21/336 ,  H01L31/119

CPC classification number: H01L29/66628 ,  H01L29/66636

Abstract: An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

Abstract translation: 可以为金属氧化物半导体场效应晶体管形成外延沉积的源极/漏极延伸。 可以形成牺牲层并蚀刻掉在栅电极下方的底切。 然后，可以沉积外延硅的源极/漏极延伸部，以在栅电极的边缘下延伸。 结果，可以通过控制牺牲材料的蚀刻来控制源极/漏极延伸在栅极下延伸的程度。 其厚度和深度可以通过控制沉积过程来控制。 此外，可以独立于后续形成的深度或重掺杂源极/漏极结的特性来控制源极/漏极延伸的特性。