公开(公告)号：US20130059434A1

公开(公告)日：2013-03-07

申请号：US13509722

申请日：2011-11-29

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Xiaobin He ,  Yihong Lu

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Xiaobin He ,  Yihong Lu

IPC: H01L21/28

CPC classification number: H01L29/66606 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials.

Abstract translation: 本发明提供了一种用于在栅极最后工艺中同时制造栅电极和接触导线的方法，包括以下步骤：在衬底上的层间电介质层中形成栅极沟槽; 在栅极沟槽和层间电介质层上形成填充层; 蚀刻填充层和层间电介质层以暴露衬底，从而形成源极/漏极接触孔; 去除填充层以暴露栅极沟槽和源极/漏极接触孔; 在源极/漏极接触孔中形成金属硅化物; 在栅极沟槽中沉积栅极电介质层和金属栅极; 在栅极沟槽和源极/漏极接触孔中填充金属; 并平坦化填充的金属。 根据本发明的制造方法，栅极电极线将由与接触孔相同的金属材料制成，使得两者可以通过一个CMP工艺制造。 这样的设计一方面简化了工艺集成的复杂性，另一方面通过CMP工艺大大加强了缺陷的控制，从而避免了不同金属材料之间可能产生的侵蚀和凹陷等缺陷。

公开(公告)号：US20130037859A1

公开(公告)日：2013-02-14

申请号：US13321852

申请日：2011-08-12

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

IPC: H01L27/10 ,  H01L21/326 ,  H01L23/522 ,  H01L29/788 ,  H01L29/92 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

Abstract translation: 提供了半导体器件及其编程方法。 半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。 本发明有利于提高TSV应用的灵活性。

公开(公告)号：US20120273886A1

公开(公告)日：2012-11-01

申请号：US13380828

申请日：2011-08-12

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

Abstract translation: 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US20120190188A1

公开(公告)日：2012-07-26

申请号：US13379967

申请日：2011-02-28

Applicant: Chao Zhao ,  Wenwu Wang ,  Huicai Zhong

Inventor： Chao Zhao ,  Wenwu Wang ,  Huicai Zhong

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a gap includes: providing a semiconductor substrate, at least having an metal interconnect layer and an insulating dielectric layer on top of the underlying metal interconnect layer, the insulating dielectric layer having a gap; forming a diffusion bather layer and a seed layer sequentially in the gap and on a surface of the insulating dielectric layer outside the gap; forming a mask layer on a surface of the seed layer outside of the gap; and depositing a metal layer on the semiconductor substrate with the mask layer, the metal layer filling the gap.

Abstract translation: 用于填充间隙的方法包括：提供至少在下面的金属互连层的顶部上具有金属互连层和绝缘介电层的半导体衬底，绝缘介电层具有间隙; 在所述间隙中的间隙和所述绝缘介电层的表面上顺序地形成扩散洗礼层和种子层; 在所述间隙的外侧的种子层的表面上形成掩模层; 以及用所述掩模层在所述半导体衬底上沉积金属层，所述金属层填充所述间隙。

公开(公告)号：US20120181586A1

公开(公告)日：2012-07-19

申请号：US13379120

申请日：2011-04-22

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/66643 ,  H01L29/7839

Abstract: The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

Abstract translation: 本发明公开了一种通过门最后工艺制造的新型MOSFET器件及其实现方法，该器件包括：衬底; 栅极叠层结构位于衬底的沟道区上，其任一侧消除了传统隔离间隔物; 构成源极/漏极区域的外延生长的超薄金属硅化物。 其中该器件消除了传统隔离间隔物下面的高电阻区域; 在源极/漏极和沟道区之间形成具有经过离子注入的掺杂剂偏析区域，这降低了金属硅化物源极/漏极与沟道之间的肖特基势垒高度。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US20120156873A1

公开(公告)日：2012-06-21

申请号：US13063922

申请日：2011-01-27

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong

IPC: H01L21/28

CPC classification number: H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

Abstract translation: 一种用于限制金属硅化物向通道区域的横向侵入的方法，包括：提供半导体衬底，形成在半导体衬底上的栅堆叠，形成在栅叠层一侧的半导体中的源区， 漏极区域形成在栅极堆叠的另一侧上的半导体衬底中; 在所述栅极堆叠和所述半导体衬底上形成牺牲隔离物; 沉积用于覆盖半导体衬底，栅极堆叠和牺牲隔离物的金属层; 对所述半导体基板进行热处理，由此使所述金属层与所述源极区域和所述漏极区域中的所述牺牲隔离物和所述半导体基板反应; 去除牺牲间隔物，牺牲间隔物和金属层的反应产物，以及不与牺牲间隔物反应的金属层的一部分。

公开(公告)号：US20120149181A1

公开(公告)日：2012-06-14

申请号：US13201125

申请日：2011-02-25

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC: H01L21/24

CPC classification number: H01L21/3221

Abstract: There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.

Abstract translation: 提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。 根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

公开(公告)号：US20120139047A1

公开(公告)日：2012-06-07

申请号：US13380096

申请日：2011-02-27

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/47 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/7839

Abstract: Disclosed is a semiconductor device, comprising a substrate, a channel region in the substrate, source/drain regions on both sides of the channel region, a gate structure on the channel region, and gate sidewall spacers formed on the sidewalls of the gate structure, characterized in that each of the source/drain regions comprises an epitaxially grown metal silicide region, and dopant segregation regions are formed at the interfaces between the epitaxially grown metal silicide source/drain regions and the channel region. By employing the semiconductor device and the method for manufacturing the same according to embodiments of the present invention, the Schottkey Barrier Height of the MOSFETs with epitaxially grown ultrathin metal silicide source/drain may be lowered, thereby improving the driving capability.

Abstract translation: 公开了一种半导体器件，包括衬底，衬底中的沟道区域，沟道区两侧的源极/漏极区域，沟道区域上的栅极结构以及形成在栅极结构的侧壁上的栅极侧壁间隔物， 其特征在于，每个源极/漏极区域包括外延生长的金属硅化物区域，并且在外延生长的金属硅化物源极/漏极区域和沟道区域之间的界面处形成掺杂剂偏析区域。 通过采用根据本发明的实施例的半导体器件及其制造方法，可以降低具有外延生长的超薄金属硅化物源极/漏极的MOSFET的肖特基势垒高度，从而提高驱动能力。

公开(公告)号：US07730238B1

公开(公告)日：2010-06-01

申请号：US11539399

申请日：2006-10-06

Applicant: Ambalavanar Arulambalam ,  Jian-Guo Chen ,  Nevin C. Heintze ,  Qian Gao Xu ,  Jun Chao Zhao

Inventor： Ambalavanar Arulambalam ,  Jian-Guo Chen ,  Nevin C. Heintze ,  Qian Gao Xu ,  Jun Chao Zhao

IPC: G06F3/00 ,  G06F5/00 ,  H04L12/28

CPC classification number: G06F5/06 ,  G06F2205/064 ,  G11B20/10527 ,  G11B27/005 ,  G11B2020/10629 ,  G11B2020/10638 ,  G11B2020/10731 ,  G11B2020/10962 ,  H04L47/10 ,  H04L47/29 ,  H04L49/90 ,  H04L49/9047

Abstract: A method comprises providing a free buffer pool in a memory including a non-negative number of free buffers that are not allocated to a queue for buffering data. A request is received to add one of the free buffers to the queue. One of the free buffers is allocated to the queue in response to the request, if the queue has fewer than a first predetermined number of buffers associated with a session type of the queue. One of the free buffers is allocated to the queue, if a number of buffers in the queue is at least as large as the first predetermined number and less than a second predetermined number associated with the session type, and the number of free buffers is greater than zero.

Abstract translation: 一种方法包括在存储器中提供一个空闲缓冲池，该存储器包括不分配给用于缓冲数据的队列的非负数的空闲缓冲器。 接收到一个请求，将一个空闲缓冲区添加到队列中。 如果队列具有少于与队列的会话类型相关联的第一预定数量的缓冲区，那么响应于该请求，将一个空闲缓冲区分配给队列。 如果队列中的多个缓冲器至少与第一预定数量一样大并且小于与会话类型相关联的第二预定数量，则空闲缓冲器中的一个被分配给队列，并且空闲缓冲器的数量更大 比零。

公开(公告)号：US20050202222A1

公开(公告)日：2005-09-15

申请号：US11124303

申请日：2005-05-06

Applicant: Eduard Cartier ,  Jerry Chen ,  Chao Zhao

Inventor： Eduard Cartier ,  Jerry Chen ,  Chao Zhao

IPC: C01G27/00 ,  C01G27/02 ,  C23C16/40 ,  C23C16/44 ,  H01B3/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  C04B35/48 ,  B32B9/00

CPC classification number: H01L21/02194 ,  C01G27/02 ,  C01P2002/72 ,  C23C16/40 ,  C23C16/405 ,  C23C16/4412 ,  H01B3/10 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02356 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L28/40 ,  H01L29/517 ,  H01L29/518 ,  Y10T428/24917 ,  Y10T428/265

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract translation: 公开了包含HfO 2 N 2和第二化合物的介电材料组合物。 组合物的特征在于至少一部分组合物为立方晶相。 此外，公开了包含这种介电材料化合物的基于半导体的器件及其形成方法。