公开(公告)号：US08409899B2

公开(公告)日：2013-04-02

申请号：US13025681

申请日：2011-02-11

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

IPC: H01L29/72

CPC classification number: H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract translation: 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。

公开(公告)号：US08232651B2

公开(公告)日：2012-07-31

申请号：US13343422

申请日：2012-01-04

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard L. Rassel

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard L. Rassel

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/485 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L2224/05553 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Abstract translation: 一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。 电子封装在接合焊盘区域和有源电路区域之间配备有边缘密封，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有 接合垫

公开(公告)号：US08077240B2

公开(公告)日：2011-12-13

申请号：US12107825

申请日：2008-04-23

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC: H04N3/14 ,  H04N5/335 ,  H04N9/64 ,  H01L31/062 ,  H01L31/113

CPC classification number: H04N5/361 ,  H04N5/359

Abstract: The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

Abstract translation: 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像质量可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

公开(公告)号：US20110193146A1

公开(公告)日：2011-08-11

申请号：US13089234

申请日：2011-04-18

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe

IPC: H01L27/146 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14643

Abstract: A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.

Abstract translation: 像素传感器结构，制造方法和操作方法。 公开了一种缓冲像素单元，其包括用于防止杂散电荷载流子到达暗电流校正像素单元的阻挡区域。 缓冲像素单元位于暗电流校正像素单元附近，并且缓冲像素单元类似于有源像素单元。 因此，围绕暗电流校正像素单元的环境与有源像素单元周围的环境相似。

公开(公告)号：US07977711B2

公开(公告)日：2011-07-12

申请号：US12172305

申请日：2008-07-14

Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC: H01L27/148 ,  H01L31/062

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract translation: 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US20110129955A1

公开(公告)日：2011-06-02

申请号：US13025681

申请日：2011-02-11

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

IPC: H01L31/0232

CPC classification number: H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract translation: 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。

公开(公告)号：US20100289082A1

公开(公告)日：2010-11-18

申请号：US12464206

申请日：2009-05-12

Applicant: James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

Inventor： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

IPC: H01L27/088 ,  H01L21/266 ,  H01L21/8234

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

Abstract translation: 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型杂质注入到衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

公开(公告)号：US07824961B2

公开(公告)日：2010-11-02

申请号：US12353549

申请日：2009-01-14

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/70

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20100245644A1

公开(公告)日：2010-09-30

申请号：US12553457

申请日：2009-09-03

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

IPC: H04N5/335 ,  H01L27/00

CPC classification number: H04N5/37452 ,  H01L27/14609 ,  H04N5/35581 ,  H04N5/3575

Abstract: A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.

Abstract translation: 包括列电路的像素传感器单元，用于制造包括列电路的像素传感器单元的设计结构和用于操作包括列电路的像素传感器单元的方法基于多个参考数据点和信号数据点对的测量 从可变电容的浮动扩散。 通过排除或包括传输栅极晶体管电容以及浮动扩散电容来提供可变电容。 这种可变电容为包括列电路的像素传感器单元提供了可变的动态范围。

公开(公告)号：US20100084690A1

公开(公告)日：2010-04-08

申请号：US12634898

申请日：2009-12-10

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC: H01L27/148 ,  H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

Abstract translation: 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。