公开(公告)号：US20180113614A1

公开(公告)日：2018-04-26

申请号：US15665246

申请日：2017-07-31

申请人： NETLIST, INC.

发明人： Hyun Lee ,  Sheng Wang

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F3/061 ,  G06F3/0644 ,  G06F3/0646 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068

摘要： A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.

公开(公告)号：US20180095908A1

公开(公告)日：2018-04-05

申请号：US15820076

申请日：2017-11-21

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F13/16 ,  G11C8/18 ,  G06F3/06

CPC分类号： G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

摘要： A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data/strobe signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit includes a data path corresponding to each data signal line in the corresponding set of data/strobe signal lines, and a command processing circuit configured to decode module control signals from the module control circuit and to control the data path in accordance with the module control signals. The data path corresponding to the each data signal line includes at least one tristate buffer controlled by the command processing circuit and a delay circuit configured to delay a signal through the data path by an amount determined by the command processing circuit in response to at least one of the module control signals.

公开(公告)号：US09858215B1

公开(公告)日：2018-01-02

申请号：US14715486

申请日：2015-05-18

申请人： Netlist, Inc.

发明人： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC分类号： G06F13/16 ,  G11C7/10 ,  G11C15/00 ,  G06F13/42

CPC分类号： G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

摘要： A memory module is operable to communicate data with a memory controller via a memory bus in response to memory commands received from the memory controller. The memory module comprises a plurality of memory integrated circuits arranged in ranks and including at least one first memory integrated circuit in a first rank and at least one second memory integrated circuit in a second rank, and further comprises a buffer coupled between the at least one first memory integrated circuit and the memory bus and between the at least one second memory integrated circuit and the memory bus. The memory module further comprises logic providing first control signals to the buffer to enable communication of a first data burst between the memory controller and the at least one first memory integrated circuit through the buffer in response to a first memory command, and providing second control signals to the buffer to enable communication of a second data burst between the at least one second memory integrated circuit and the memory bus through the buffer in response to a second memory command.

公开(公告)号：US09824035B2

公开(公告)日：2017-11-21

申请号：US15426064

申请日：2017-02-07

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C8/18

CPC分类号： G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

摘要： A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

公开(公告)号：US09606907B2

公开(公告)日：2017-03-28

申请号：US13970606

申请日：2013-08-20

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F12/00 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12

CPC分类号： G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

摘要： A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

公开(公告)号：US09436600B2

公开(公告)日：2016-09-06

申请号：US14302292

申请日：2014-06-11

申请人： Netlist, Inc.

发明人： Hyun Lee

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0815 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/621

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

摘要翻译： 具有多通道易失性存储器子系统的存储器系统耦合到非易失性存储器子系统以提供独立的，可配置的数据备份。 易失性存储器子系统具有使用诸如DRAM存储器的易失性存储器形式的一个或多个主存储器模块，NV子系统为其提供选择性持久备份。 主内存模块是使用DDR SDRAM内存设备的双列直插式内存模块或DIMM。 非易失性存储器子系统（NV备份）包括NV控制器和非易失性存储器NVM。 NV备份还可以包括一个内存缓存，以帮助处理和存储数据。 在某些实施例中，NV控制器和非易失性存储器经由相关联的信号线耦合到主存储器的一个或多个DIMM通道。 这样的信号线可以是例如母板上的迹线，并且可以包括用于传送数据，地址和/或控制信号的一个或多个信号总线。 NV控制器和非易失性存储器可以安装在主板上。

公开(公告)号：US20160202749A1

公开(公告)日：2016-07-14

申请号：US14994829

申请日：2016-01-13

申请人： NetList, Inc.

发明人： Scott H. Milton

IPC分类号： G06F1/30 ,  G06F11/14

CPC分类号： G06F1/30 ,  G06F11/1441 ,  G06F11/1458 ,  G06F11/2015 ,  G06F2201/81 ,  G06F2201/86

摘要： A memory system is described. The memory system includes one or more memory subsystems. The memory system also includes a power module coupled with at least one of the one or more memory subsystems. Further, the memory system includes a controller coupled with the one or more memory subsystems and the power module. The controller is configured to generate an energy threshold based on energy used for a backup operation.

摘要翻译： 描述了存储器系统。 存储器系统包括一个或多个存储器子系统。 存储器系统还包括与所述一个或多个存储器子系统中的至少一个耦合的电源模块。 此外，存储器系统包括与一个或多个存储器子系统和功率模块耦合的控制器。 控制器被配置为基于用于备份操作的能量来生成能量阈值。

公开(公告)号：US20160196223A1

公开(公告)日：2016-07-07

申请号：US14840865

申请日：2015-08-31

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F3/06

CPC分类号： G06F13/28 ,  G06F1/185 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F13/4027 ,  G06F13/4243 ,  G06F2212/205 ,  G06F2212/7208 ,  G11C7/1072 ,  G11C14/0018

摘要： A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.

公开(公告)号：US20160019138A1

公开(公告)日：2016-01-21

申请号：US14706873

申请日：2015-05-07

申请人： Netlist, Inc.

发明人： Hyun Lee

IPC分类号： G06F12/02 ,  G06F12/06 ,  G11C7/10

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/068 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0871 ,  G06F12/0897 ,  G06F13/10 ,  G06F13/28 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C7/1072

摘要： A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller reads first data from the non-volatile memory subsystem in response to a Flash access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory bus.

摘要翻译： 存储器模块包括被配置为耦合到计算机系统中的存储器通道并且能够用作计算机系统的主存储器的非易失性存储器子系统，为计算机系统提供存储的非易失性存储器子系统，以及耦合到 易失性存储器子系统，非易失性存储器子系统和C / A总线。 模块控制器响应于经由存储器通道接收到的闪存访问请求从非易失性存储器子系统读取第一数据，并且使得至少一部分第一数据被写入到易失性存储器子系统中以响应于虚拟写入 通过C / A总线接收存储器命令。 模块控制装置包括由计算机系统通过存储器总线可访问的状态寄存器。

公开(公告)号：US20150248249A1

公开(公告)日：2015-09-03

申请号：US14489281

申请日：2014-09-17

申请人： Netlist, Inc.

发明人： Mike Hossein Amidi ,  Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1441 ,  G06F11/1612 ,  G06F2212/7208

摘要： Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

摘要翻译： 存储在易失性存储器子系统中的数据被冗余地备份到非易失性存储器子系统的第一和第二通道中。 在检测到指示实际或即将发生的功率损耗或减少的触发条件并且多个副本被存储在专用非易失性存储器通道中时，从易失性存储器子系统检索数据。 存储的副本可能会被错误检查和更正，并在必要时重新写入。 可以随后从非易失性存储器子系统中检索冗余备份的数据，进行纠错，并将无错误的副本传送到易失性存储器子系统。