公开(公告)号：US20050099847A1

公开(公告)日：2005-05-12

申请号：US11008531

申请日：2004-12-10

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： G11C16/00 ,  G06K17/00 ,  G06K19/077 ,  G11C11/34 ,  G11C14/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

公开(公告)号：US20050023601A1

公开(公告)日：2005-02-03

申请号：US10928193

申请日：2004-08-30

申请人： Yuji Takeuchi ,  Riichiro Shirota

发明人： Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： G11C16/02 ,  G11C16/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  H01L27/115

摘要： A semiconductor device with a non-volatile memory, having: first to fourth memory cells arranged in a first direction; a first bit line extending over the first memory cell in a second direction and connected to the second memory cell; a second bit line extending over the second memory cell in the second direction and connected to the first memory cell; a third bit line extending over the third memory cell in the second direction and connected to the third memory cell; and a fourth bit line extending over the fourth memory cell in the second direction and connected to the fourth memory cell.

摘要翻译： 一种具有非易失性存储器的半导体器件，具有：沿第一方向布置的第一至第四存储器单元; 第一位线，沿着第二方向在第一存储单元上延伸并连接到第二存储器单元; 第二位线在第二方向上延伸到第二存储器单元上并连接到第一存储器单元; 第三位线，沿着第二方向在第三存储单元上延伸并连接到第三存储器单元; 以及在所述第四方向上延伸到所述第四存储器单元上并连接到所述第四存储器单元的第四位线。

公开(公告)号：US20050013169A1

公开(公告)日：2005-01-20

申请号：US10920161

申请日：2004-08-18

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C7/00 ,  G11C11/56 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

摘要翻译： NAND单元单元包括串联连接的多个存储单元。 对所有存储单元进行擦除操作。 然后，将与在擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并将11V施加到控制栅极 的剩余存储单元。 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US06781895B1

公开(公告)日：2004-08-24

申请号：US09722474

申请日：2000-11-28

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/34 ,  G11C29/52

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

公开(公告)号：US06611010B2

公开(公告)日：2003-08-26

申请号：US09726582

申请日：2000-12-01

申请人： Akira Goda ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Riichiro Shirota ,  Seiichi Aritome

发明人： Akira Goda ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Riichiro Shirota ,  Seiichi Aritome

IPC分类号： H01L2710

CPC分类号： H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.

摘要翻译： 在位线接触部分中，通过氧化硅膜形成接触孔，并且在接触孔中埋设由掺杂杂质的多晶硅膜制成的接触塞。 氧化硅膜形成有与接触孔重叠的布线槽。 由金属膜制成的位线埋在布线槽中。 接触插塞延伸穿过位线，并且其上表面与位线的上表面基本上共面。 接触插塞仅在其侧面与位线接触。

公开(公告)号：US06590255B2

公开(公告)日：2003-07-08

申请号：US09916595

申请日：2001-07-30

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

公开(公告)号：US06534867B1

公开(公告)日：2003-03-18

申请号：US09670990

申请日：2000-09-26

申请人： Eiji Kamiya ,  Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Yuji Takeuchi ,  Norihisa Arai

发明人： Eiji Kamiya ,  Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Yuji Takeuchi ,  Norihisa Arai

IPC分类号： H01L2348

CPC分类号： H01L27/11526 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/78

摘要： A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

摘要翻译： 半导体器件包括：半导体衬底; 多个具有低杂质浓度的第一扩散层，所述第一扩散层形成在所述半导体衬底的表面上; 多个具有高杂质浓度的第二扩散层，所述第二扩散层形成在所述半导体衬底的表面上; 多个第一触点，每个接触第一扩散层，并且每一个都由半导体形成; 以及多个第二触点，每个第二触点与第二扩散层接触，并且每个都由金属形成。

公开(公告)号：US06208560B1

公开(公告)日：2001-03-27

申请号：US09599397

申请日：2000-06-22

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C1606

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20 V is applied to the control gate of any selected one of the memory cells, 0 V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11 V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

摘要翻译： 包括串联连接的多个存储单元的NAND单元单元。 对所有存储单元进行擦除操作。 然后，对所有存储单元施加与施加在擦除操作中的擦除电压极性相反的软编程电压，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到存储单元中的任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到 剩余存储单元的控制门。 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US06172911B2

公开(公告)日：2001-01-09

申请号：US09283583

申请日：1999-04-01

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G11C1606

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

公开(公告)号：US6117729A

公开(公告)日：2000-09-12

申请号：US97152

申请日：1998-06-12

申请人： Hirohisa Iizuka ,  Shinji Satoh ,  Riichiro Shirota

发明人： Hirohisa Iizuka ,  Shinji Satoh ,  Riichiro Shirota

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.

摘要翻译： 用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置 多个NAND存储器单元。 用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。