公开(公告)号：US20060072035A1

公开(公告)日：2006-04-06

申请号：US11237959

申请日：2005-09-29

Applicant: Young-ho Lee ,  Seung-joon Yang

Inventor： Young-ho Lee ,  Seung-joon Yang

IPC: H04N7/01

CPC classification number: H04N7/0115 ,  H04N5/253 ,  H04N19/132 ,  H04N19/427 ,  H04N19/587 ,  H04N19/85

Abstract: An image processing device and method to select a field to use in interpolation, if an input image is a film image. The image processing device includes a field selector to select a field to use to interpolate a current field based on difference values in field data among first, second, and third fields being consecutively input in an input image, the field to use to interpolate the current image being one of the first and the third fields and the current field being the second field, a film detector to generate a pattern based on the difference values in the field data between the first, second, and third fields and to determine whether the input image is a film image based on the generated pattern, and an interpolator to interpolate the second field using the one of the first and third field selected by the field selector if the film detector determines the input image to be a film image. Accordingly, when the input image is a film image without a bad-edit, the interpolation process is executed by selecting two temporarily consecutive fields of a field to be interpolated, and using the field with a smaller difference values in field data from the field to be interpolated and a problem of judder in images can be resolved.

Abstract translation: 如果输入图像是胶片图像，则选择要在插值中使用的场的图像处理装置和方法。 图像处理装置包括场选择器，用于基于在输入图像中连续输入的第一，第二和第三场中的场数据中的差值来选择用于内插当前场的场，所述场用于内插当前场 图像是第一和第三场中的一个，当前场是第二场，膜检测器，用于基于第一场，第二场和第三场之间的场数据中的差值生成模式，并确定输入 图像是基于所生成的图案的胶片图像，以及内插器，如果胶片检测器将输入图像确定为胶片图像，则使用场选择器选择的第一和第三场中的一个来内插第二场。 因此，当输入图像是没有不良编辑的胶片图像时，通过选择要插值的场的两个临时连续的场来执行内插处理，并且使用来自场的场数据中具有较小差值的场 被插值，可以解决图像抖动问题。

公开(公告)号：US20050214434A1

公开(公告)日：2005-09-29

申请号：US10510700

申请日：2004-03-12

Applicant: Dong-Hun Yoon ,  Gi-Wang Han ,  Soon-Gi Hong ,  Young-Ho Lee

Inventor： Dong-Hun Yoon ,  Gi-Wang Han ,  Soon-Gi Hong ,  Young-Ho Lee

IPC: A23D9/013 ,  A23L1/30 ,  A61K8/06 ,  A61K8/37 ,  A61K31/23 ,  A61Q19/06 ,  C11C3/08 ,  C11C3/10 ,  C12P7/64 ,  A23D7/00

CPC classification number: A61K8/67 ,  A23D9/013 ,  A23L33/115 ,  A23V2002/00 ,  A61K8/06 ,  A61K8/375 ,  A61K31/23 ,  A61Q19/06 ,  C11C3/08 ,  C11C3/10 ,  C12P7/6472 ,  A61K2300/00 ,  A23V2250/1866 ,  A23V2250/194 ,  A23V2250/182 ,  A23V2250/192

Abstract: A fat composition of high purity diglyceride containing conjugated linoleic acid and a preparation method thereof are provided. The fat composition comprises 85% to 99.9% by weight of diglyceride containing 0.1 to 80% by weight of conjugated linoleic acid, and the balance being monoglyceride, triglyceride or a mixture thereof. The fat composition can be used in highly functional food additives owing to conjugated linoleic acid having various functions of effecting anti-cancer activity, reducing human body fat, enhancing immunogenicity, and preventing and/or treating diabetes, and can be simply prepared at a high production yield.

Abstract translation: 提供含有共轭亚油酸的高纯度甘油二酯的脂肪组合物及其制备方法。 脂肪组合物包含85重量％至99.9重量％的含有0.1-80重量％共轭亚油酸的甘油二酯，其余为单酸甘油酯，甘油三酯或其混合物。 脂肪组合物可以用于高功能食品添加剂中，这是因为共轭亚油酸具有各种具有抗癌活性，降低人体脂肪，增强免疫原性，以及预防和/或治疗糖尿病的功能，并且可以简单地制备成高 产量。

公开(公告)号：US20050105825A1

公开(公告)日：2005-05-19

申请号：US10962900

申请日：2004-10-13

Applicant: Hwa-sup Lim ,  Young-ho Lee

Inventor： Hwa-sup Lim ,  Young-ho Lee

IPC: G06T15/00 ,  G06K9/32 ,  G06K9/36 ,  G06T3/40

CPC classification number: G06T3/403 ,  G06T3/4007

Abstract: An image processing device and a method thereof. The image processing device includes a mapper to map a two-dimensional plane of an input image into a three-dimensional vector surface, a coefficient calculator to calculate a coefficient with respect to an equation of a plane formed by a plurality of pixels mapped by the mapper, and an interpolator to interpolate by calculating a gray-level of a location to be interpolated based on the equation of the plane obtained by the coefficient calculator. When the pixels on the 2-D plane are mapped into the 3-D vector space, the image processing device according to an exemplary embodiment of the present general inventive concept prevents overshoot or undershoot which may occur at the edges or on planes, and thus displays a smooth image.

Abstract translation: 一种图像处理装置及其方法。 图像处理装置包括将输入图像的二维平面映射成三维矢量面的映射器，计算与由多个像素映射的多个像素形成的平面的方程式的系数的系数计算部 映射器和内插器，用于通过基于由系数计算器获得的平面的方程式计算要插值的位置的灰度级来插值。 当2-D平面上的像素被映射到3-D向量空间中时，根据本发明总体构思的示例性实施例的图像处理装置防止可能发生在边缘或平面上的过冲或下冲，因此 显示平滑的图像。

公开(公告)号：US20160099170A1

公开(公告)日：2016-04-07

申请号：US14943532

申请日：2015-11-17

Applicant: Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

Inventor： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

IPC: H01L21/768 ,  H01L27/24 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Abstract translation: 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

公开(公告)号：US08686563B2

公开(公告)日：2014-04-01

申请号：US12639542

申请日：2009-12-16

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US08483349B2

公开(公告)日：2013-07-09

申请号：US12181891

申请日：2008-07-29

Applicant: Jae-Yong Kim ,  Hyung-Kyu Kim ,  Kyung-Ho Yoon ,  Young-Ho Lee ,  Kang-Hee Lee

Inventor： Jae-Yong Kim ,  Hyung-Kyu Kim ,  Kyung-Ho Yoon ,  Young-Ho Lee ,  Kang-Hee Lee

IPC: G21C3/34

CPC classification number: G21C3/02 ,  G21C3/322 ,  G21C3/352 ,  G21C3/356 ,  Y02E30/38

Abstract: A spacer grid for dual-cooling nuclear fuel rods arranged at a narrow interval. The spacer grid solves the problem in which, since the dual-cooling nuclear fuel rods are used to improve the cooling performance and stability of nuclear fuel and obtain high burnup and output, the outer diameter of each dual-cooling nuclear fuel rod is increased, and thus the gap between each dual-cooling nuclear fuel rod and the grid strap is decreased. The spacer grid includes first grid straps and second grid straps, which are crossed and arranged in transverse and longitudinal directions at regular intervals and have the shape of a flat strip, and support structures, which are fitted into the first and second grid straps around intersections of the first and second grid straps so as to support the dual-cooling nuclear fuel rods.

Abstract translation: 用于双冷却核燃料棒的隔离栅格，其间隔狭窄。 间隔栅格解决了由于双冷核燃料棒用于提高核燃料的冷却性能和稳定性并获得高燃耗和输出的问题，每个双重冷却核燃料棒的外径增加， 因此，每个双重冷却核燃料棒和网格带之间的间隙减小。 间隔网格包括第一网格带和第二网格带，它们以横向和纵向方向以规则的间隔交叉并布置，并且具有平坦的形状和支撑结构，其被安装在交叉点周​​围的第一和第二网格带中 的第一和第二格栅带，以支撑双重冷却核燃料棒。

公开(公告)号：US20130072022A1

公开(公告)日：2013-03-21

申请号：US13678930

申请日：2012-11-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US08243872B2

公开(公告)日：2012-08-14

申请号：US12146493

申请日：2008-06-26

Applicant: Kang-Hee Lee ,  Hyung-Kyu Kim ,  Kyung-Ho Yoon ,  Young-Ho Lee ,  Jae-Yong Kim ,  Tae-Hyun Chun ,  Wang-Kee In ,  Dong-Seok Oh ,  Chang-Hwan Shin

Inventor： Kang-Hee Lee ,  Hyung-Kyu Kim ,  Kyung-Ho Yoon ,  Young-Ho Lee ,  Jae-Yong Kim ,  Tae-Hyun Chun ,  Wang-Kee In ,  Dong-Seok Oh ,  Chang-Hwan Shin

IPC: G21C3/34

CPC classification number: G21C3/352 ,  G21C3/322 ,  G21C3/3563 ,  Y02E30/38

Abstract: A spacer grid can be applied to close-spaced nuclear fuel rods. The spacer grid is directed to solve the problem in which, as the outer diameter of each nuclear fuel rod increases due to the use of dual-cooled nuclear fuel rods for improving cooling performance and obtaining high combustion and high output power, the gap between the neighboring nuclear fuel rods is narrowed to thus make it impossible to use an existing spacer grid. The spacer grid is a combination of unit grid straps, each of which has supports for supporting each of the nuclear fuel rods set in a narrow array and has a sheet shape, which are combined with each other. The supports are located at positions shifted from the longitudinal central line of each unit grid strap toward sub-channels.

Abstract translation: 间隔栅格可以应用于紧密间隔的核燃料棒。 针对这种间隔格栅来解决这样一个问题，即由于使用双冷核燃料棒来提高冷却性能并获得高燃烧和高输出功率，因此每个核燃料棒的外径增加 相邻的核燃料棒变窄，因此不可能使用现有的间隔栅格。 间隔栅格是单元网格带的组合，每个网格带都具有支撑，用于支撑以窄阵列设置的每个核燃料棒，并且具有彼此组合的片状。 支撑件位于从每个单元格栅带的纵向中心线向子通道移位的位置。

公开(公告)号：US20120178234A1

公开(公告)日：2012-07-12

申请号：US13324035

申请日：2011-12-13

Applicant: Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

Inventor： Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

IPC: H01L21/8239

CPC classification number: H01L27/0629 ,  H01L27/11531 ,  H01L28/20

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract translation: 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

公开(公告)号：US20120132976A1

公开(公告)日：2012-05-31

申请号：US13368556

申请日：2012-02-08

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L29/788 ,  H01L29/06

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。