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公开(公告)号：US09703748B2
公开(公告)日：2017-07-11
申请号：US14459731
申请日：2014-08-14
Applicant: Apple Inc.
Inventor： Michael J. Smith , Josh P. de Cesare , Brijesh Tripathi , Derek Iwamoto , Shane J Keil
CPC classification number: G06F13/4226 , G06F13/105 , G06F13/28 , G06F13/385 , G06F13/4022 , G06F13/4059
Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.
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公开(公告)号：US09691349B2
公开(公告)日：2017-06-27
申请号：US14676544
申请日：2015-04-01
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Guy Cote
CPC classification number: G09G5/02 , G09G5/363 , G09G5/391 , G09G2340/0428 , G09G2360/02
Abstract: Systems, apparatuses, and methods for passing source pixel data through a display control unit. A display control unit includes N-bit pixel component processing lanes for processing source pixel data. When the display control unit receives M-bit source pixel components, wherein ‘M’ is greater than ‘N’, the display control unit may assign the M-bit source pixel components to the N-bit processing lanes. Then, the M-bit source pixel components may passthrough the pixel component processing elements of the display control unit without being modified.
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73.发明授权公开(公告)号：US09619377B2
公开(公告)日：2017-04-11
申请号：US14458949
申请日：2014-08-13
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US20160307540A1
公开(公告)日：2016-10-20
申请号：US14691353
申请日：2015-04-20
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi , Guy Cote
IPC: G09G5/02
CPC classification number: G09G5/14 , G09G5/026 , G09G2320/0242 , G09G2320/0666 , G09G2320/0673 , G09G2340/06 , G09G2360/18
Abstract: Systems, apparatuses, and methods for performing linear scaling in a display control unit. A display control unit receives source image data that has already been gamma encoded with an unknown gamma value. The display control unit includes a hard-coded LUT storing a gamma curve of a first gamma value which is used to perform a degamma operation on the received source image data. Even if the first gamma value used to perform the degamma operation is different from the gamma value used to gamma encode the source image data, fewer visual artifacts are generated as compared with not performing a degamma operation. After the degamma operation is performed, the source image data may be linearly scaled.
Abstract translation: 用于在显示控制单元中执行线性缩放的系统，装置和方法。 显示控制单元接收已经用未知伽马值进行伽马编码的源图像数据。 显示控制单元包括硬编码LUT，其存储用于对所接收的源图像数据执行去角度运算的第一伽玛值的伽马曲线。 即使用于进行反伽马操作的第一伽马值与用于对源图像数据进行伽玛编码的伽马值不同，与不进行除血操作相比，产生较少的视觉伪影。 在执行去雾操作之后，可以线性地缩放源图像数据。
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公开(公告)号：US09471955B2
公开(公告)日：2016-10-18
申请号：US14309645
申请日：2014-06-19
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi , Dinesh M. Shedge
CPC classification number: G06T1/60 , G06F3/1438 , G06T1/20 , G09G5/399 , G09G2310/0221 , G09G2352/00 , G09G2360/06
Abstract: Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. To ensure synchronization between the two display pipelines, a repeat vertical blanking interval (VBI) signal is generated if either of the display pipelines has not already received the frame packet with configuration data for the next frame. When the repeat VBI signal is generated, both display pipelines will repeat processing of the current frame.
Abstract translation: 用多个显示管道驱动分割显示的系统，设备和方法。 用于驱动显示器的框架被逻辑地分为多个部分，第一显示管道驱动显示器的第一部分，第二显示管线驱动显示器的第二部分。 为了确保两个显示管道之间的同步，如果显示管道中的任一个还没有接收到具有下一帧的配置数据的帧分组，则生成重复垂直消隐间隔（VBI）信号。 当产生重复VBI信号时，两条显示管道将重复对当前帧的处理。
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Patent Agency Ranking
公开(公告)号：US20150346001A1
公开(公告)日：2015-12-03
申请号：US14458885
申请日：2014-08-13
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。
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公开(公告)号：US09158350B2
公开(公告)日：2015-10-13
申请号：US13717941
申请日：2012-12-18
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Colin Whitby-Strevens , Geertjan Joordens , Moon Jung Kim , Raman S Thiara
CPC classification number: G06F1/26 , G09G5/00 , G09G5/006 , G09G5/18 , G09G2330/021 , G09G2370/10
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。
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78.发明授权公开(公告)号：US09153212B2
公开(公告)日：2015-10-06
申请号：US13850548
申请日：2013-03-26
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Albert C. Kuo
CPC classification number: G09G5/395 , G06F3/14 , G09G5/001 , G09G5/393 , G09G2330/02 , G09G2330/021 , G09G2340/02 , G09G2360/121
Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.
Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为响应于检测输出帧中的静态内容而压缩输出帧并将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。
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公开(公告)号：US09013493B2
公开(公告)日：2015-04-21
申请号：US13718142
申请日：2012-12-18
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Colin Whitby-Strevens , Geertjan Joordens , Moon Jung Kim , Raman S Thiara
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。
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公开(公告)号：US20140198117A1
公开(公告)日：2014-07-17
申请号：US14218011
申请日：2014-03-18
Applicant: Apple Inc.
Inventor： Anup K. Sharma , Scott P. Krueger , James M. Hollabaugh , Roberto G. Yepez , Brijesh Tripathi , Jeffrey J. Terlizzi , Terry L. Tikalsky
CPC classification number: G06F3/1431 , G06F3/14 , G06F13/385 , G06F13/4013 , G06F13/4018 , G06T1/60 , Y02D10/14 , Y02D10/151
Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.
Abstract translation: 在一个实施例中，主计算设备包括内部显示器，并且还包括连接到外部显示器的连接器。 提供电缆连接到连接器并连接到外部显示器。 电缆包括视频处理功能。 例如，电缆可以包括被配置为存储帧缓冲器的存储器。 帧缓冲器可以存储视频数据的帧，以供视频处理设备在电缆中进一步处理。 视频处理设备可以以各种方式来操纵帧，例如， 缩放，旋转，伽马校正，抖动校正等
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