公开(公告)号：US20060154463A1

公开(公告)日：2006-07-13

申请号：US10905590

申请日：2005-01-12

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/3205

CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

摘要翻译： 使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。 金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。 然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

公开(公告)号：US20060103818A1

公开(公告)日：2006-05-18

申请号：US10904601

申请日：2004-11-18

申请人： Steven Holmes ,  Mark Hakey ,  Toshiharu Furukawa ,  David Horak

发明人： Steven Holmes ,  Mark Hakey ,  Toshiharu Furukawa ,  David Horak

IPC分类号： G03B27/42 ,  G03F7/20

CPC分类号： G03F7/70341 ,  G03F7/70925

摘要： A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.

公开(公告)号：US20060073682A1

公开(公告)日：2006-04-06

申请号：US10711764

申请日：2004-10-04

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/28

CPC分类号： H01L21/02115 ,  B82Y10/00 ,  H01L21/02282 ,  H01L21/3146 ,  H01L21/3185 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76888 ,  H01L2221/1047

摘要： A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

摘要翻译： 用于制造半导体器件的低k电介质材料，使用低k电介质材料的半导体结构，以及形成这种介电材料和制造这种结构的方法。 低k介电材料包括碳纳米结构，如碳纳米管或碳​​棒球，其特征在于绝缘电子状态。 碳纳米结构可以在包含碳纳米结构的层在基底上形成之前或之后转变为绝缘电子状态。 将碳纳米结构转化为绝缘电子态的一种方法是氟化。

公开(公告)号：US20060073394A1

公开(公告)日：2006-04-06

申请号：US10711758

申请日：2004-10-04

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： G03C5/00 ,  G06F17/50 ,  G03F1/00

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.

摘要翻译： 提供了组合的宽图像和环形切割器图案，用于在通过减少数量的光刻步骤的侧壁成像技术形成的基板上切割和形成宽图像部分到硬掩模。 形成单个掩模，其提供宽掩模部分，同时另外提供掩模以在硬掩模蚀刻期间保护下面的硬掩模的临界边缘。 在将硬掩模切割成部分之后，除去后续掩模的保护部分以暴露下面的硬掩模的临界边缘，​​同时保持限定宽图像部分所需的形状。 因此，可以以减少的步数形成硬掩模切割，硬掩模临界边缘保护和大面积掩模。

公开(公告)号：US06998332B2

公开(公告)日：2006-02-14

申请号：US10754073

申请日：2004-01-08

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  William H-L Ma

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  William H-L Ma

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/2815

摘要： Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.

摘要翻译： 公开了一种在基板上形成导电层并在导电层上方形成牺牲结构的方法。 接下来，本发明使用能够经历尺寸变化的间隔物材料形成邻近牺牲结构的侧壁间隔，此后本发明在将侧壁间隔物留在适当位置的情况下去除牺牲结构。 然后，本发明使用牺牲掩模保护所选择的侧壁间隔物，并且使侧壁间隔物中的其它侧壁隔离件不被保护。 这允许本发明选择性地将未受保护的侧壁间隔物暴露于改变未受保护的侧壁间隔物的尺寸的处理。 这导致未受保护的侧壁间隔件具有与受保护的侧壁间隔物不同的尺寸。 然后，本发明移除牺牲掩模，并且使用侧壁间隔物作为栅极导体掩模来图案化导电层，以在衬底上产生不同尺寸的栅极导体。 接下来，本发明移除侧壁间隔物并形成与栅极导体相邻的源极，漏极和沟道区域。

公开(公告)号：US20050245008A1

公开(公告)日：2005-11-03

申请号：US10709314

申请日：2004-04-28

申请人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/44 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

CPC分类号： H01L21/823437 ,  H01L21/28097 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/4975

摘要： A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

摘要翻译： 用于形成半导体器件的栅极结构的方法包括在衬底上限定导电牺牲结构，在导电牺牲结构的侧壁上形成反应的金属膜，以及去除导电牺牲结构的未反应部分。

公开(公告)号：US20050242378A1

公开(公告)日：2005-11-03

申请号：US11175582

申请日：2005-07-06

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

摘要翻译： 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

公开(公告)号：US06960510B2

公开(公告)日：2005-11-01

申请号：US10187579

申请日：2002-07-01

申请人： Sadanand V. Deshpande ,  Toshiharu Furukawa ,  David V. Horak ,  Wesley C. Natzle ,  Akihisa Sekiguchi ,  Len Y. Tsou ,  Qingyun Yang

发明人： Sadanand V. Deshpande ,  Toshiharu Furukawa ,  David V. Horak ,  Wesley C. Natzle ,  Akihisa Sekiguchi ,  Len Y. Tsou ,  Qingyun Yang

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8236

CPC分类号： H01L21/26586 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/2815 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144

摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.

摘要翻译： 提供了形成具有亚光刻尺寸的结构的方法。 该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

公开(公告)号：US20050227498A1

公开(公告)日：2005-10-13

申请号：US10814482

申请日：2004-03-31

申请人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

发明人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/469

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US06940134B2

公开(公告)日：2005-09-06

申请号：US10064316

申请日：2002-07-02

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/76 ,  H01L27/088

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/485 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

摘要： Methods of forming a contact to a gate electrode or substrate despite misalignment of the contact opening due to lithographic techniques, and a semiconductor having such a contact. Silicide can be created on the gate and/or diffusion using the invention.

摘要翻译： 尽管由于平版印刷技术而导致接触开口的对准而形成与栅电极或基板的接触的方法，以及具有这种接触的半导体。 可以使用本发明在门和/或扩散上产生硅化物。