公开(公告)号：US09443945B2

公开(公告)日：2016-09-13

申请号：US14600097

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L27/01 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

公开(公告)号：US09425318B1

公开(公告)日：2016-08-23

申请号：US14633351

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Gerd Zschaetzsch

IPC: H01L21/324 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L21/02 ,  H01L27/108 ,  H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成堆叠在衬底上的叠层。 堆叠包括硅锗层和硅层，其中硅锗层具有第一锗浓度。 堆叠被冷凝以在锗层中产生第二锗浓度，其中第二锗浓度大于第一锗浓度。 形成包括叠层的翅片，并且形成覆盖在翅片上的浇口。

公开(公告)号：US09401423B2

公开(公告)日：2016-07-26

申请号：US13943521

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L21/30 ,  H01L21/3115 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864

Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—potentially in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.

Abstract translation: 当用氘增强的栅极电介质和应变通道区形成晶体管时，可以使用在晶体管上方形成的应变诱导电介质材料层的制造工艺来有效地将氘引入和扩散到栅极电介质。 应变诱导电介质材料层中的氘结合可以在沉积过程中基于沉积过程中完成沉积过程，其中氘存在于工艺环境中。 可以选择沉积工艺的工艺温度来执行 - 潜在地与进一步随后执行的工艺步骤组合 - 氘到栅极电介质的充分扩散。

公开(公告)号：US09368506B2

公开(公告)日：2016-06-14

申请号：US14741528

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Pablo Mikalo ,  Stefan Flachowsky

IPC: G11C11/34 ,  H01L27/115 ,  G11C16/04 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一阱和第二阱间隔开并掺杂有第一导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。

公开(公告)号：US09324831B2

公开(公告)日：2016-04-26

申请号：US14461713

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/66575 ,  H01L29/66651

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract translation: 公开了用于形成没有间隔物的栅极和所得到的器件的方法。 实施例可以包括在衬底上形成沟道层; 在通道层上形成一个虚拟栅极; 在沟道层上形成层间电介质（ILD）并围绕虚拟栅极; 通过去除虚拟栅极以下的虚拟栅极和沟道层，在ILD和沟道层内形成沟槽; 在沟槽的底部形成未掺杂沟道区; 以及在沟槽内的未掺杂沟道区上方形成栅极。

公开(公告)号：US09231045B2

公开(公告)日：2016-01-05

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。

公开(公告)号：US09218976B2

公开(公告)日：2015-12-22

申请号：US13965860

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Gerd Zschaetzsch ,  Jan Hoentschel

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L21/28097 ,  H01L21/8238 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/6659

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 然而，完全硅化的栅极的形成受到源极和漏极区域以及栅极电极的硅化同时正常执行的事实的阻碍。 所要求保护的方法提出了两个相互连接的硅化过程。 在第一硅化工艺期间，形成金属硅化物，形成与源区和漏区的界面，而不影响栅电极。 在第二硅化处理期间，形成与栅电极具有界面的金属硅化物层，而不会影响晶体管的源极和漏极区域。

公开(公告)号：US09209274B2

公开(公告)日：2015-12-08

申请号：US13946103

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschaetzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.

Abstract translation: 本公开在各方面提供了形成半导体器件的方法，形成半导体器件结构的方法，半导体器件和半导体器件结构。 在本文的一些说明性实施例中，栅极结构形成在设置在基板的表面上的半导体材料的非平面表面部分上。 掺杂的间隔物形成材料形成在栅极结构上，并且半导体材料和并入掺杂的间隔物形成材料中的掺杂剂被扩散到靠近半导体材料的表面的半导体材料中，以形成源极/漏极延伸区域。 制造的半导体器件可以是多栅极器件，并且例如包括finFET和/或wireFET。

公开(公告)号：US20150214116A1

公开(公告)日：2015-07-30

申请号：US14165107

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/8238 ,  H01L21/266 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract translation: 提供一种形成半导体器件的方法，包括以下步骤：形成第一和第二PMOS晶体管器件，其中第一PMOS晶体管器件为低标准或高电压阈值晶体管器件，而第二PMOS晶体管器件为超高电压阈值晶体管器件 并且其中形成所述第一PMOS晶体管器件包括注入掺杂剂以形成所述第一PMOS晶体管器件的源极和漏极结，并且在注入所述掺杂剂之后执行所述第一PMOS晶体管器件的热退火，以及形成所述第二PMOS晶体管器件包括注入掺杂剂 以在第一PMOS晶体管器件进行热退火之后形成第二PMOS晶体管器件的源极和漏极结。

公开(公告)号：US09082876B2

公开(公告)日：2015-07-14

申请号：US13842103

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/38 ,  H01L21/8238 ,  H01L21/266

CPC classification number: H01L21/823807 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在制造集成电路的方法的实施例中，在半导体衬底上形成P型栅电极结构和N型栅电极结构。 栅电极结构各自包括覆盖在栅极电介质层上的栅电极和覆盖在栅电极上的氮化物盖。 使用P型栅极电极结构和N型栅极电极结构作为掩模将电导率确定离子注入到半导体衬底中，以形成用于P型栅电极结构和N型栅极的源极区和漏极区 电极结构。 在将导电性确定离子注入半导体衬底期间，氮化物盖保持覆盖在N型栅电极结构上，以形成用于N型栅电极结构的源区和漏区。