公开(公告)号：US09362279B1

公开(公告)日：2016-06-07

申请号：US14609171

申请日：2015-01-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Andy Wei ,  William James Taylor ,  Ryan Ryoung-han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/417

CPC分类号： H01L27/0886 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/66545

摘要： A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material. The resulting structure has replacement (conductive) gates, conductive material above the N and P type epitaxy, and a contact to the conductive material for each of N and P type epitaxy.

摘要翻译： 公开了接触形成方法和结构。 该方法包括提供起始半导体结构，该结构包括具有耦合到基板的翅片的半导体基板，翅片的底部被第一介电层包围，覆盖每个翅片的一部分的虚拟栅极，间隔件和 每个虚拟栅极的盖，以及延伸到第一介电层并暴露第一介电层的栅极之间的衬里沟槽。 该方法还包括在沟槽中的相邻散热片之间产生硬掩模材料的外延屏障，在邻近屏障相对侧的鳍片上产生N和P型外延材料，并在N和P型外延材料上产生牺牲半导体外延， 使得随后的去除可以对N型和P型外延材料选择性地进行。 所得结构具有替代（导电）栅极，N和P型外延上方的导电材料，以及N和P型外延中的每一个与导电材料的接触。

公开(公告)号：US09337101B1

公开(公告)日：2016-05-10

申请号：US14674549

申请日：2015-03-31

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Hoon Kim ,  Chanro Park ,  Ruilong Xie

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC分类号： H01L21/823431 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823481

摘要： One illustrative method disclosed herein includes, among other things, forming a plurality of fins in a semiconducting substrate, each of which has a corresponding masking layer feature positioned thereabove, forming a masking layer that has an opening that exposes at least two fins of the plurality of fins, performing an angled etching process through the opening in the masking layer so as to remove the masking layer feature formed above one of the at least two exposed fins, and thereby define an exposed fin, while leaving the masking layer feature intact above the other of the at least two exposed fins, and performing an anisotropic etching process through the opening in the masking layer to remove the exposed fin while leaving the other of the at least two exposed fins intact.

摘要翻译： 本文中公开的一种说明性方法包括在半导体衬底中形成多个翅片，每个鳍状物具有位于其上方的对应掩模层特征，形成掩模层，掩模层具有暴露至少两个散热片的开口 的翅片，通过掩模层中的开口进行成角度的蚀刻工艺，以去除在至少两个暴露的翅片之一上形成的掩模层特征，从而限定出露出的翅片，同时将掩模层特征保留在 至少两个暴露的翅片中的另一个，并且通过掩模层中的开口进行各向异性蚀刻处理以去除暴露的翅片，同时保持至少两个暴露的翅片中的另一个。

公开(公告)号：US09236309B2

公开(公告)日：2016-01-12

申请号：US14687300

申请日：2015-04-15

申请人： GLOBALFOUNDRIES INC.

发明人： Chanro Park ,  Steven Bentley

IPC分类号： H01L21/20 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/161

CPC分类号： H01L21/823431 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/161 ,  H01L29/165

摘要： Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.

摘要翻译： 提供制造一个或多个半导体鳍片结构的方法，其包括：提供包括第一半导体材料的衬底结构; 在所述衬底结构上方提供散热片堆叠，所述散热片堆叠包括至少一个包括第二半导体材料的半导体层; 在所述散热片堆叠和所述基板结构上沉积保形膜; 以及使用至少部分地将所述散热片堆叠作为掩模来蚀刻所述衬底结构，以便于限定所述一个或多个半导体鳍片结构。 共形保护膜在蚀刻衬底结构期间保护散热片堆叠的至少一个半导体层的侧壁免受蚀刻。 作为一个示例，第一半导体材料可以是或包括硅，第二半导体材料可以是或包括硅锗，并且在一个示例中，保形膜可以是氮化硅。

公开(公告)号：US09178035B1

公开(公告)日：2015-11-03

申请号：US14459446

申请日：2014-08-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L21/3213

CPC分类号： H01L29/66545 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/7833

摘要： One method of forming replacement gate structures for first and second devices, the first device being a short channel device and the second device being a long channel device, is disclosed which includes forming a first and a second gate cavity above a semiconductor substrate, the first gate cavity being narrower than the second gate cavity, forming a bulk metal layer within the first and second gate cavities, performing an etching process to recess the bulk metal layer within the first and second gate cavities, resulting in the bulk metal layer within the second gate cavity being at its final thickness, forming a masking layer over the bulk metal layer within the second gate cavity, and performing an etching process to further recess the bulk metal layer within the first gate cavity, resulting in the bulk metal layer within the first gate cavity being at its final thickness.

摘要翻译： 公开了一种形成第一和第二器件的替代栅极结构的方法，第一器件是短沟道器件，第二器件是长沟道器件，其包括在半导体衬底上形成第一和第二栅极腔，第一器件 栅极腔比第二栅极腔窄，在第一和第二栅极空腔内形成体金属层，执行蚀刻工艺以使第一和第二栅极空腔内的体金属层凹陷，导致第二栅极腔内的体金属层 栅极腔处于其最终厚度，在第二栅极腔内的体金属层上形成掩模层，并且执行蚀刻工艺以进一步使第一栅极腔内的体金属层凹陷，导致第一栅极腔内的主体金属层 门腔处于其最终厚度。

公开(公告)号：US08835244B2

公开(公告)日：2014-09-16

申请号：US13773397

申请日：2013-02-21

申请人： GlobalFoundries, Inc. ,  International Business Machines Corporation

发明人： Ruilong Xie ,  Chanro Park ,  Shom Ponoth

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/66477 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/788

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底上提供牺牲栅极结构。 牺牲栅极结构在两个间隔物之间​​包括两个间隔物和牺牲栅极材料。 该方法将牺牲栅极材料的一部分凹入两个间隔物之间​​。 在使用牺牲栅极材料作为掩模的同时蚀刻两个间隔物的上部区域。 该方法包括去除牺牲栅极材料的剩余部分并暴露两个间隔物的下部区域。 第一金属沉积在两个间隔物的下部区域之间。 第二金属沉积在两个间隔物的上部区域之间。

公开(公告)号：US11069677B2

公开(公告)日：2021-07-20

申请号：US16941423

申请日：2020-07-28

申请人： GLOBALFOUNDRIES INC.

发明人： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC分类号： H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L49/02

摘要： We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US20200052088A1

公开(公告)日：2020-02-13

申请号：US16594276

申请日：2019-10-07

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/768 ,  H01L21/764

摘要： A device is disclosed that includes an active layer, a gate structure positioned above a channel region of the active layer and a first sidewall spacer positioned adjacent the gate structure. The device also includes a gate cap layer positioned above the gate structure and an upper spacer that contacts sidewall surfaces of the gate cap layer, a portion of an upper surface of the gate structure and an inner surface of the first sidewall spacer.

公开(公告)号：US10529826B1

公开(公告)日：2020-01-07

申请号：US16101876

申请日：2018-08-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC分类号： H01L29/66 ,  H01L21/764 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

摘要： A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in the gate cavity, recessing the first dielectric layer and the sidewall spacer to expose sidewall surfaces of the cap layer, removing the inner spacer to define a first spacer cavity, forming an upper spacer in the spacer cavity and contacting sidewall surfaces of the cap layer, forming a second dielectric layer above the upper spacer and the cap layer, and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.

公开(公告)号：US10468300B2

公开(公告)日：2019-11-05

申请号：US15641927

申请日：2017-07-05

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

摘要： A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

公开(公告)号：US10373873B1

公开(公告)日：2019-08-06

申请号：US15933708

申请日：2018-03-23

申请人： GLOBALFOUNDRIES INC.

发明人： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Laertis Economikos

IPC分类号： H01L21/8234 ,  H01L29/66

摘要： Gate isolation methods and structures for a FinFET device leverage the definition and formation of a gate cut opening within a sacrificial gate layer prior to patterning the sacrificial gate layer to form a sacrificial gate. The gate cut opening formed in the sacrificial gate layer is filled with a sacrificial isolation layer. After forming source/drain junctions over source/drain regions of a fin, the sacrificial isolation layer is replaced with an isolation layer, and the sacrificial gate is replaced with a functional gate.