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    Two level memory full line writes
    74.
    发明授权
    Two level memory full line writes 有权

    公开(公告)号：US09619396B2

    公开(公告)日：2017-04-11

    申请号：US14670857

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/00 ,  G06F12/0891

    CPC classification number: G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126 ,  G06F2212/1016

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

    TWO LEVEL MEMORY FULL LINE WRITES
    76.
    发明申请
    TWO LEVEL MEMORY FULL LINE WRITES 有权
    两级记忆全线写

    公开(公告)号：US20160283388A1

    公开(公告)日：2016-09-29

    申请号：US14670857

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126 ,  G06F2212/1016

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

    Abstract translation: 存储器控制器接收存储器无效请求，该存储器无效请求引用具有远存储器和近存储器的两级系统存储器拓扑中的远存储器行，标识对应于该行的近存储器的地址，并且在地址处读取数据以确定是否 该行的副本在近内存中。 如果数据包含远端存储器的另一行的副本，而另一行的副本是脏的，则该地址的数据将被刷新到远端存储器。 发送内存无效请求的完成以指示相干代理被授予对该行的独占访问权限。 通过独占访问，将修改该行以生成行的修改版本，并且将使用修改版本的行覆盖近端存储器的地址。

    SPECULATIVE READS IN BUFFERED MEMORY
    77.
    发明申请
    SPECULATIVE READS IN BUFFERED MEMORY 有权
    缓冲存储器中的分析读数

    公开(公告)号：US20160179679A1

    公开(公告)日：2016-06-23

    申请号：US14582121

    申请日：2014-12-23

    Applicant: Intel Corporation

    Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Yen-Cheng Liu

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026

    Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

    Abstract translation: 通过用于与特定地址相关联的数据的缓冲存储器访问链路从主机设备接收推测读请求。 发送读取请求以将数据发送到存储器设备。 响应于读取请求从存储器装置接收数据，并且接收到的数据作为对在推测性读取请求之后接收的请求读取请求的响应被发送到主机设备。

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