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公开(公告)号：US09477568B2
公开(公告)日：2016-10-25
申请号：US14039047
申请日：2013-09-27
Applicant: International Business Machines Corporation
Inventor： Malcolm S. Allen-Ware , Jon A. Casey , Sungjun Chun , Alan J. Drake , Charles R. Lefurgy , Karthick Rajamani , Jeonghee Shin , Thomas A. Wassick , Victor Zyuban
CPC classification number: G06F11/3006 , G06F11/004 , G06F11/0703 , G06F11/3027 , G06F11/3058 , G06F11/3093
Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
Abstract translation: 提供了一种用于确定一组多核处理器中的一组核心中的一组互连组的建模年龄的机制。 对于多核处理器集合中的一组核心中的一组互连组中的每个互连组，确定互连组的当前建模年龄。 然后确定用于该组互连组的互连组的至少一个当前建模年龄是否大于寿命终止值。 响应于互连组的至少一个当前建模年龄大于寿命终止值，发送与至少一个相关联的互连组采取校正动作的指示。
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公开(公告)号：US09323301B2
公开(公告)日：2016-04-26
申请号：US13773841
申请日：2013-02-22
Applicant: International Business Machines Corporation
Inventor： Malcolm S. Allen-Ware , Bishop Brock , Tilman Gloekler , Timothy G. Hallett , Charles R. Lefurgy , Karthick Rajamani , Guillermo J. Silva , Gregory S. Still
CPC classification number: G06F1/26 , G06F1/3296 , Y02D10/172
Abstract: Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.
Abstract translation: 计算系统电压控制方法包括接收第一性能状态的指示。 第一性能状态与第一电压相关联并且应用于至少一个计算系统组件。 由第一计算系统组件从第二计算系统组件接收第一性能状态的指示。 接收第二性能状态的指示，其中第二性能状态与不等于第一电压的第二电压相关联。 确定第二性能状态是否在由最低性能状态和最大性能状态限定的范围内。 响应于确定第二性能状态在由最小性能状态和最大性能状态限定的范围内的情况下，将至少一个计算系统组件的电压设置为等于与第二执行状态相关联的电压。
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公开(公告)号：US09310424B2
公开(公告)日：2016-04-12
申请号：US13775502
申请日：2013-02-25
Applicant: International Business Machines Corporation
Inventor： Malcolm S. Allen-Ware , Ronald J. Bolam , Alan J. Drake , Charles R. Lefurgy , Barry P. Linder , Steven W. Mittl , Karthick Rajamani
CPC classification number: G01R31/2851
Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.
Abstract translation: 提供了一种用于确定多核处理器的建模年龄的机制。 对于多核处理器中的一组核心中的每个核心，确定一组降级和一组电压域的规则间隔的温度，电压和频率，从而形成建模年龄 多核处理器。 确定多核处理器的建模年龄是否大于寿命终止值。 响应于多核处理器的建模年龄大于寿命终止值，发出多核处理器需要更换的指示。
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公开(公告)号：US09310397B2
公开(公告)日：2016-04-12
申请号：US13752668
申请日：2013-01-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Karthick Rajamani , Juan C. Rubio , Michael A. Schappert
CPC classification number: G01R15/142 , G01R15/183
Abstract: A sensor array including multiple current sensors provides input for power measurement and management systems. The sensor array includes split ferrite cylinder portions connected by a frame, so that when the array is installed around multiple branch circuits in a power distribution panel or raceway, the ferrite cylinders are completed to surround the conductor(s) of the associated branch circuit. Voltage sensing may also be incorporated within the sensors by providing an electrically conductive plate, wire or other element that capacitively couples to the corresponding wire(s).
Abstract translation: 包括多个电流传感器的传感器阵列为功率测量和管理系统提供输入。 传感器阵列包括通过框架连接的分离的铁氧体圆筒部分，使得当阵列安装在配电盘或滚道中的多个分支电路周围时，完成铁氧体磁体以包围相关联的分支电路的导体。 通过提供电容耦合到相应的导线的导电板，导线或其它元件，电压感测也可以并入传感器内。
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公开(公告)号：US09286959B2
公开(公告)日：2016-03-15
申请号：US14082624
申请日：2013-11-18
Applicant: International Business Machines Corporation
Inventor： Alexandre P. Ferreira , Jente B. Kuang , Janani Mukundan , Karthick Rajamani
CPC classification number: G11C8/12 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
Abstract: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
Abstract translation: 提供了一种存储器，其包括被配置成多个小金库的一组非易失性存储器单元。 可以独立且独立于非易失性存储单元组中的其他小金库启用多个小组中的每个小钞。 存储器还包括耦合到非易失性存储器阵列的存储体组合的外围电路组电路，其被配置为使能在所述多个小组内的所选小组内的位线的选定子集。 此外，存储器包括耦合到外围小金属电路的小金库选择电路，其被配置为选择与所选择的小金库相关联的数据，以从该小钞中读出或写入该小钞。
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Patent Agency Ranking
公开(公告)号：US09250666B2
公开(公告)日：2016-02-02
申请号：US13686391
申请日：2012-11-27
Applicant: International Business Machines Corporation
Inventor： Irving Baysah , John S. Dodson , Karthick Rajamani , Eric E. Retter , Gregory S. Still , Malcolm S. Allen-Ware , Scot H. Rider , Todd J. Rosedahl , Gary Van Huben
CPC classification number: G06F1/26 , G06F1/206 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F11/3037 , G06F11/3409 , Y02D10/11 , Y02D10/16
Abstract: A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector.
Abstract translation: 具有用于系统管理的可扩展数据收集的系统包括多个本地数据收集器和系统收集器。 每个本地数据采集器与系统的相应子系统耦合。 每个本地数据收集器被配置为周期性地从相应的子系统收集功率管理相关数据，并且格式化收集的功率管理相关数据，以便沿着本地数据采集器和系统收集器之间的多个通道中的任一个传送。 系统收集器经由多个通道与多个本地数据收集器耦合。 系统收集器至少部分地基于信道状态从系统收集器和每个本地数据收集器之间的信道中选择，并且沿着所选择的信道检索由每个本地数据收集器收集的功率管理相关数据，用于 本地数据收集器。
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公开(公告)号：US20150338910A1
公开(公告)日：2015-11-26
申请号：US14286148
申请日：2014-05-23
Applicant: International Business Machines Corporation
Inventor： Malcolm S. Allen-Ware , Shawn P. Authement , Charles R. Lefurgy , Karthick Rajamani , Andrew D. Walls
CPC classification number: G06F12/0246 , G06F1/206 , G06F1/3206 , G06F1/3225 , G06F12/02 , G06F2212/7206
Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.
Abstract translation: 提供了一种用于闪存存储系统中的动态功率和热封的机制。 接收闪存存储系统的一组测量值，该组测量值包括一组当前（I）测量值，一组电压（V）测量值或一组温度（T ）测量值。 来自当前（I）测量集合的平均电流（Iavg）值，并且响应于平均电流（Iavg）值大于预定最大电流（Imax）值，确定是否 闪存存储系统的擦除操作大于预定的最小擦除率。 响应于对于闪存存储系统执行擦除操作的速率大于预定最小擦除速率的速率，对闪存存储系统执行擦除操作的速率减小预定值。
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公开(公告)号：US20150268710A1
公开(公告)日：2015-09-24
申请号：US14219550
申请日：2014-03-19
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Michael S. Floyd , Heather L. Hanson , Hans M. Jacobson , Karthick Rajamani , Srinivasan Ramani , Todd J. Rosedahl , Augusto J. Vega
CPC classification number: G06F9/5094 , G06F1/3243 , Y02D10/152
Abstract: According to an aspect, power management of a multi-core processing system includes determining workload characteristics in the multi-core processing system. A power adjustment scenario is identified based on the workload characteristics. A predetermined actuation order for at least two power adjustment actuators is identified based on the power adjustment scenario. Based on the predetermined actuation order, it is determined whether there is an adequate adjustment capacity for a power adjustment action associated with one of the at least two power adjustment actuators. The power adjustment action is initiated based on the predetermined actuation order and determining that the adequate adjustment capacity is available.
Abstract translation: 根据一个方面，多核处理系统的功率管理包括确定多核处理系统中的工作负载特性。 基于工作负载特征识别功率调整情景。 基于功率调节场景来识别用于至少两个功率调节致动器的预定的致动顺序。 基于预定的致动顺序，确定是否存在与至少两个功率调节致动器中的一个相关联的功率调节动作的适当调节能力。 功率调节动作基于预定的启动顺序开始，并确定适当的调整容量可用。
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公开(公告)号：US09081606B2
公开(公告)日：2015-07-14
申请号：US13675546
申请日：2012-11-13
Applicant: International Business Machines Corporation
Inventor： Gary D. Carpenter , Stefanie R. Chiras , Alexandre P. Ferreira , Jente B. Kuang , Karthick Rajamani , Freeman L. Rawson, III
CPC classification number: G06F9/466 , G06F12/1416 , G06F13/00
Abstract: A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction.
Abstract translation: 处理器包括处理器核心，高速缓存和跟踪器。 处理器核心被配置为执行持久写入指令并接收完成的持久写入指令的通知。 跟踪器被配置为跟踪持久写入指令的完成状态。
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公开(公告)号：US20150094995A1
公开(公告)日：2015-04-02
申请号：US14039047
申请日：2013-09-27
Applicant: International Business Machines Corporation
Inventor： Malcolm S. Allen-Ware , Jon A. Casey , Sungjun Chun , Alan J. Drake , Charles R. Lefurgy , Karthick Rajamani , Jeonghee Shin , Thomas A. Wassick , Victor Zyuban
IPC: G06F11/30
CPC classification number: G06F11/3006 , G06F11/004 , G06F11/0703 , G06F11/3027 , G06F11/3058 , G06F11/3093
Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
Abstract translation: 提供了一种用于确定一组多核处理器中的一组核心中的一组互连组的建模年龄的机制。 对于多核处理器集合中的一组核心中的一组互连组中的每个互连组，确定互连组的当前建模年龄。 然后确定用于该组互连组的互连组的至少一个当前建模年龄是否大于寿命终止值。 响应于互连组的至少一个当前建模年龄大于寿命终止值，发送与至少一个相关联的互连组采取校正动作的指示。
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