公开(公告)号：US20160188423A1

公开(公告)日：2016-06-30

申请号：US15073699

申请日：2016-03-18

Applicant: International Business Machines Corporation

Inventor： Patrick J. Meaney ,  Glenn D. Gilda ,  Eric E. Retter ,  John S. Dodson ,  Gary A. Van Huben ,  Brad W. Michael ,  Stephen J. Powell

IPC: G06F11/14 ,  G11C7/10 ,  G11C29/52 ,  G06F11/16

CPC classification number: G06F11/1679 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/32 ,  G06F11/1497 ,  G06F11/1604 ,  G06F11/1675 ,  G06F13/1689 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract translation: 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。

公开(公告)号：US20160188398A1

公开(公告)日：2016-06-30

申请号：US15072659

申请日：2016-03-17

Applicant: International Business Machines Corporation

Inventor： Glenn D. Gilda ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  John S. Dodson

IPC: G06F11/07 ,  G06F11/16

CPC classification number: G06F11/1662 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/0757 ,  G06F11/1044 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2007 ,  G06F13/1673

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract translation: 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括接收与至少一个信道相关联的失步指示的方法。 存储器控制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段到期，恢复多个信道上的业务，并验证 同步在第二时间段重新建立。

公开(公告)号：US09318171B2

公开(公告)日：2016-04-19

申请号：US14501107

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Gary A. Van Huben ,  Patrick J. Meaney ,  John S. Dodson ,  Scot H. Rider ,  James C. Gregerson ,  Eric E. Retter ,  Irving G. Baysah ,  Glenn D. Gilda ,  Lawrence D. Curley ,  Vesselina K. Papazova

IPC: G06F13/00 ,  G06F13/28 ,  G11C7/22 ,  G06F13/42 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4076

CPC classification number: G11C7/222 ,  G06F13/1673 ,  G06F13/42 ,  G11C5/04 ,  G11C7/225 ,  G11C11/4076

Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

Abstract translation: 用于存储器子系统中的双异步和同步存储器操作的计算机系统实现方法包括在存储器控制器和存储器缓冲器芯片之间建立同步通道。 模式选择器基于存储器缓冲器芯片的操作模式确定存储器缓冲器芯片的存储器域锁相环的参考时钟源。 基于同步的操作模式，将嵌套域锁相环的输出作为参考时钟源提供给存储器缓冲器芯片中的存储器域锁相环。 嵌套域锁相环可与存储器控制器的存储器控​​制器锁相环同步操作。 提供单独的参考时钟，独立于嵌套域锁相环作为基于异步操作模式的存储器域锁相环的参考时钟。

公开(公告)号：US09142272B2

公开(公告)日：2015-09-22

申请号：US13835521

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Gary A. Van Huben ,  Patrick J. Meaney ,  John S. Dodson ,  Scot H. Rider ,  James C. Gregerson ,  Eric E. Retter ,  Irving G. Baysah ,  Glenn D. Gilda ,  Lawrence D. Curley ,  Vesselina K. Papazova

IPC: G06F9/26 ,  G11C7/22 ,  G06F13/42 ,  G11C5/04 ,  G11C11/4076

CPC classification number: G11C7/222 ,  G06F13/1673 ,  G06F13/42 ,  G11C5/04 ,  G11C7/225 ,  G11C11/4076

Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.

Abstract translation: 实施例涉及双异步和同步存储器系统。 一个方面是一种系统，其包括存储器控制器和经由同步信道耦合到存储器控制器的存储器缓冲器芯片。 存储器缓冲器芯片包括被配置为与嵌套域中的存储器控​​制器同步通信的存储器缓冲器单元和被配置为与存储器域中的至少一个存储器接口端口通信的存储器缓冲适配器。 所述至少一个存储器接口端口可操作以访问至少一个存储器设备。 边界层连接到嵌套域和存储域，其中边界层可配置为在嵌套和存储器域之间以同步传输模式操作并且在嵌套和存储器域之间以异步传输模式操作。

公开(公告)号：US20150262706A1

公开(公告)日：2015-09-17

申请号：US14211288

申请日：2014-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence D. Curley ,  Patrick J. Meaney ,  George C. Wellwood

IPC: G11C29/10 ,  G06F11/07 ,  G06F11/263

CPC classification number: G11C29/10 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/2635 ,  G06F12/0607 ,  G11C5/04 ,  G11C29/18 ,  G11C29/20 ,  G11C2029/0409 ,  G11C2029/1806

Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

Abstract translation: 实施例包括组合的等级和线性存储器地址递增实用程序。 一个方面包括适用于作为中央处理单元（CPU）芯片的集成子系统的存储器控​​制器内实现的地址递增实用程序。 在这种片上实施例中，地址递增实用程序利用专用硬件，驻留芯片的固件和一个或多个存储器地址配置图来提高处理速度，效率和精度。 组合的等级和线性存储器地址递增实用程序被设计为有效地递增遍历所有单个位地址，以便逐级地划分为多个等级的大逻辑存储器空间。 地址增加实用程序顺序地产生所选择的等级的所有顺序存储器地址，然后移动到下一个级别并且顺序地产生该等级的所有存储器地址，并且等等，直到等级被处理。

公开(公告)号：US09136987B2

公开(公告)日：2015-09-15

申请号：US13835444

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Mark R. Hodges ,  Irving G. Baysah ,  John S. Dodson ,  Patrick J. Meaney ,  Glenn D. Gilda

IPC: G06F11/00 ,  H04L1/18 ,  G06F11/16

CPC classification number: H04L1/1874 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/141 ,  G06F11/1625 ,  G11C7/1066 ,  G11C2211/4061 ,  H04L1/188

Abstract: Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.

Abstract translation: 实施例涉及在存储器系统中的重放暂停。 一个方面是包括耦合到存储器控制器接口的重放缓冲器和耦合到重放缓冲器的重放控制器和存储器控制器的系统。 重播控制被配置为接收与作为操作的一部分的从存储器控制器接口发送数据到存储器子系统相关联的错误指示。 基于错误指示将重放等待信号提供给存储器控制器。 基于等待一段足以使存储器控制器向重播缓冲器提供与该操作相关联的剩余数据的时间段，断言重放信号。

公开(公告)号：US09092312B2

公开(公告)日：2015-07-28

申请号：US13714531

申请日：2012-12-14

Applicant: International Business Machines Corporation

Inventor： Patrick J. Meaney ,  Michael B. Spear ,  Kenneth L. Wright

IPC: G06F11/00

CPC classification number: G06F11/004 ,  G06F11/221 ,  G06F11/25

Abstract: A method includes modifying, at a bit error injection circuit, a multiplier value by a first value according to an occurrence of a first event. The method also includes, in response to a determination that the modified multiplier value matches a first threshold, modifying, at the bit error injection circuit, the offset value according to an occurrence of a second event. The method further includes, in response to a determination that the modified offset value matches a second threshold, asserting, at the bit error injection circuit, an error injection signal. The method further includes asserting a first error pattern to be transmitted via a bus lane based on the error injection signal.

Abstract translation: 一种方法包括根据第一事件的发生在位错误注入电路处修改乘数值乘以第一值。 该方法还包括响应于修改的乘数值与第一阈值匹配的确定，在位错误注入电路处修改根据第二事件的发生的偏移值。 该方法还包括响应于修改的偏移值与第二阈值匹配的确定，在位错误注入电路处断言错误注入信号。 该方法还包括基于误差注入信号来确定经由总线通道发送的第一错误模式。

公开(公告)号：US09065481B2

公开(公告)日：2015-06-23

申请号：US13747842

申请日：2013-01-23

Applicant: International Business Machines Corporation

Inventor： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

IPC: G11C29/00 ,  H03M13/05 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20

CPC classification number: H03M13/05 ,  G06F11/073 ,  G06F11/1008 ,  G06F11/1064 ,  G06F11/1666 ,  G06F11/20

Abstract: A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

Abstract translation: 提供了一种错误检测技术。 控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。 控制器检测读取的字线的ECC字中的错误。 控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。 控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

公开(公告)号：US20150019905A1

公开(公告)日：2015-01-15

申请号：US14501494

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Luis A. Lastras ,  Patrick J. Meaney ,  Eldee Stephens ,  George C. Wellwood

IPC: G06F11/10

CPC classification number: G06F11/106 ,  G06F11/10

Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.

Abstract translation: 实施例涉及用于擦洗的标记通道中的过时数据检测。 一个方面包括使标记的频道在线，其中计算机包括包括标记频道的多个存储信道和剩余的多个未标记的信道。 另一方面包括对多个存储信道中的地址执行擦除读取。 另一方面包括基于通过擦除读取从未标记通道返回的数据来确定由标记通道读取的擦除数据是否有效或过时。 另一方面包括基于确定从标记频道读取的数据返回的数据是否有效，而不是对标记的频道执行擦除回写。 另一方面包括基于确定从标记通道读取的擦除返回的数据是否过时，执行校正数据的擦除回写到标记的通道。

公开(公告)号：US20150019831A1

公开(公告)日：2015-01-15

申请号：US14501107

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Gary A. Van Huben ,  Patrick J. Meaney ,  John S. Dodson ,  Scot H. Rider ,  James C. Gregerson ,  Eric E. Retter ,  Irving G. Baysah ,  Glenn D. Gilda ,  Lawrence D. Curley ,  Vesselina K. Papazova

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G06F13/1673 ,  G06F13/42 ,  G11C5/04 ,  G11C7/225 ,  G11C11/4076

Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

Abstract translation: 用于存储器子系统中的双异步和同步存储器操作的计算机系统实现方法包括在存储器控制器和存储器缓冲器芯片之间建立同步通道。 模式选择器基于存储器缓冲器芯片的操作模式确定存储器缓冲器芯片的存储器域锁相环的参考时钟源。 基于同步的操作模式，将嵌套域锁相环的输出作为参考时钟源提供给存储器缓冲器芯片中的存储器域锁相环。 嵌套域锁相环可与存储器控制器的存储器控​​制器锁相环同步操作。 提供单独的参考时钟，独立于嵌套域锁相环作为基于异步操作模式的存储器域锁相环的参考时钟。