公开(公告)号：US09177868B2

公开(公告)日：2015-11-03

申请号：US14228840

申请日：2014-03-28

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Shahab Siddiqui

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/823857 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor structure by forming an oxide layer above a substrate; optionally annealing the oxide layer to densify the oxide layer; forming a first sacrificial gate above the substrate; removing the first dummy gate; optionally annealing the first gate oxide layer; and forming a first replacement metal gate above the gate oxide layer. In some embodiments selective nitridation may be performed during the annealing step.

Abstract translation: 一种通过在衬底上形成氧化层来制造半导体结构的方法; 任选地退火氧化物层以致密化氧化物层; 在所述衬底上形成第一牺牲栅极; 去除第一虚拟门; 可选地退火第一栅极氧化物层; 以及在所述栅极氧化物层上方形成第一替代金属栅极。 在一些实施方案中，可以在退火步骤期间进行选择性氮化。

公开(公告)号：US20150279746A1

公开(公告)日：2015-10-01

申请号：US14739562

申请日：2015-06-15

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC: H01L21/8238

CPC classification number: H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

公开(公告)号：US20150255294A1

公开(公告)日：2015-09-10

申请号：US14197959

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.

Abstract translation: 本公开提供了一种形成具有减小的栅极 - 接触寄生电容的半导体器件的栅极结构的方法。 在替代栅极方案中，高k栅介质层沉积在栅极腔的底表面和侧壁上。 顺序地在高k栅极电介质层上沉积金属覆盖层和牺牲覆盖层以形成材料堆叠。 在牺牲盖层的垂直部分中离子注入之后，材料堆叠的至少部分垂直部分被去除。 随后去除牺牲帽层的剩余部分提供栅极部件结构。 栅极部件结构的垂直部分不延伸到栅极空腔的顶部，从而显着降低栅极 - 接触寄生电容。

公开(公告)号：US20150243662A1

公开(公告)日：2015-08-27

申请号：US14699264

申请日：2015-04-29

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

Abstract translation: 半导体结构具有半导体衬底和设置在衬底上的nFET和pFET。 pFET具有形成在半导体衬底的表面上或其表面上的半导体SiGe沟道区，以及覆盖沟道区的氧化物层和覆盖氧化物层的高k电介质层的栅极电介质。 栅电极覆盖在栅极电介质上，并且具有邻接高k层的下金属层，邻接下金属层的清除金属层和与清除金属层邻接的上金属层。 金属层清除了衬底（nFET）中的氧和与氧化物层的SiGe（pFET）界面，导致pFET的Tinv和Vt有效降低，同时缩放Tinv并维持nFET的Vt，导致Vt pFET变得更接近具有缩放Tinv值的类似构造的nFET的Vt。

公开(公告)号：US20150228748A1

公开(公告)日：2015-08-13

申请号：US14179121

申请日：2014-02-12

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

Abstract translation: 在半导体材料层上形成第一栅极结构和第二栅极结构。 第一栅极结构包括平面硅基栅极电介质，平面高k栅极电介质，金属氮化物部分和第一半导体材料部分，并且第二栅极结构包括硅基电介质材料部分和第二半导体 材料部分。 在形成栅极间隔物和平坦化介电层之后，用包括化学氧化物部分和第二高k栅极电介质的瞬态栅极结构来代替第二栅极结构。 可以通过更换半导体材料部分在每个栅电极中形成功函数金属层和导电材料部分。 栅电极包括平面硅基栅极电介质，平面高k栅极电介质和U形高k栅极电介质，另一个栅电极包括化学氧化物部分和另一个U形高k栅极电介质 。

公开(公告)号：US09099393B2

公开(公告)日：2015-08-04

申请号：US13959375

申请日：2013-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDARIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

Abstract translation: 一种用于半导体制造的方法包括在栅腔中的介电层上形成扩散阻挡层和含金属层中的至少一个。 执行第一退火以将元件从扩散阻挡层和含金属层中的至少一个扩散到电介质层中。 去除含金属层和扩散阻挡层。 执行第二次退火以调节介电层中的元件的扩散以提供栅极电介质区域。

公开(公告)号：US08999831B2

公开(公告)日：2015-04-07

申请号：US13680257

申请日：2012-11-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; annealing the structure at a high temperature of not less than 800° C.; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. Optionally, a second annealing step can be performed after the first anneal. This second anneal is performed as a millisecond anneal using a flash lamp or a laser.

Abstract translation: 一种制造用于半导体器件的替代栅极堆叠的方法包括在去除伪栅极之后的以下步骤：在由虚拟栅极腾出的区域上生长高k电介质层; 在高k电介质层上沉积薄金属层; 在所述薄金属层上沉积牺牲层; 在不低于800℃的高温下退火该结构; 去除牺牲层; 以及沉积用于间隙填充的低电阻率金属的金属层。 任选地，可以在第一退火之后执行第二退火步骤。 使用闪光灯或激光器作为毫秒退火来执行该第二退火。

公开(公告)号：US20150054087A1

公开(公告)日：2015-02-26

申请号：US14500914

申请日：2014-09-29

Applicant: International Business Machines Corporation ,  GLOBAL FOUNDRIES Inc

Inventor： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/02697 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.

Abstract translation: 一种CMOS器件，其在nFET部分和pFET部分之间包括nFET部分，pFET部分和层间电介质。 nFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，直接物理接触的第二氮化钛层 其中阻挡层和填充凹槽的其余部分的栅极金属。 pFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，阻挡层上的第二氮化钛层 与第二氮化钛层直接物理接触的第三氮化钛层和填充凹槽的其余部分的栅极金属。

公开(公告)号：US20140162447A1

公开(公告)日：2014-06-12

申请号：US13709250

申请日：2012-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Lisa F. Edge ,  Martin M. Frank ,  Balasubramanian S. Haran ,  Atsuro Inada ,  Sivananda K. Kanakasabapathy ,  Andreas Knorr ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Soon-cheon Seo

IPC: H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/41791

Abstract: A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括对衬底上的翅片进行图案化，在栅极堆叠的一部分上构图栅极堆叠，以及布置在衬底上的绝缘体层的一部分，在栅极叠层上形成保护屏障， 所述翅片和所述绝缘体层的一部分，所述保护屏障包围所述栅极堆叠，在所述鳍片和所述保护屏障的部分上沉积第二绝缘体层，执行第一蚀刻工艺以选择性地去除所述第二绝缘体层的部分以限定空腔 其暴露鳍片的源极和漏极区域的部分，而不明显地去除保护屏障，以及在空腔中沉积导电材料。

公开(公告)号：US11258012B2

公开(公告)日：2022-02-22

申请号：US16385179

申请日：2019-04-16

Applicant: Tokyo Electron Limited ,  International Business Machines Corporation

Inventor： Devi Koty ,  Qingyun Yang ,  Hiroyuki Miyazoe ,  Takashi Ando ,  Eduard Cartier ,  Vijay Narayanan ,  Sebastian Ulrich Englemann

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CxHyFz)-based plasma chemistry or a fluorocarbon (CxFy)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.