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1.发明申请公开(公告)号：US20170154825A1
公开(公告)日：2017-06-01
申请号：US15290410
申请日：2016-10-11
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/12 , H01L21/84 , H01L27/092 , H01L29/49
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545 , H01L29/785 , H01L29/786
摘要： An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
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2.发明申请DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE METAL DEVICES 审中-公开双金属镀层和双重栅极电压替代栅极金属器件公开(公告)号：US20140084382A1
公开(公告)日：2014-03-27
申请号：US14089982
申请日：2013-11-26
IPC分类号： H01L29/49 , H01L27/088
CPC分类号： H01L29/49 , H01L21/28088 , H01L21/82345 , H01L21/823842 , H01L27/088 , H01L29/66545
摘要： A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
摘要翻译： 公开了用于形成双金属填充物的结构和方法以及用于替换栅极金属器件的双阈值电压。 使用涉及钛和铝的选择性沉积方法来形成具有不同填充金属和不同功函数金属的两个相邻晶体管，从而能够在相邻晶体管中实现不同的阈值电压。
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3.发明申请INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE 有权使用全金属栅组合多个金属氧化物半导体的多个阈值电压装置公开(公告)号：US20150333065A1
公开(公告)日：2015-11-19
申请号：US14809236
申请日：2015-07-26
IPC分类号： H01L27/092 , H01L29/49 , H01L29/45 , H01L27/088 , H01L29/51
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译： 提供了基板，其上形成有与第一区域互补的第一区域和第二区域。 在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。 在第一区域上去除第一个全金属栅极叠层，以产生结果。 在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。 第一和第二全金属栅极堆叠被封装。
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公开(公告)号：US20150279746A1
公开(公告)日：2015-10-01
申请号：US14739562
申请日：2015-06-15
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/8238
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
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公开(公告)号：US20140162447A1
公开(公告)日：2014-06-12
申请号：US13709250
申请日：2012-12-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, INC. , RENESAS ELECTRONICS CORPORATION
发明人： Lisa F. Edge , Martin M. Frank , Balasubramanian S. Haran , Atsuro Inada , Sivananda K. Kanakasabapathy , Andreas Knorr , Vijay Narayanan , Vamsi K. Paruchuri , Soon-cheon Seo
IPC分类号： H01L21/28
CPC分类号： H01L29/66795 , H01L29/41791
摘要： A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities.
摘要翻译： 一种用于制造场效应晶体管器件的方法，包括对衬底上的翅片进行图案化，在栅极堆叠的一部分上构图栅极堆叠，以及布置在衬底上的绝缘体层的一部分，在栅极叠层上形成保护屏障， 所述翅片和所述绝缘体层的一部分，所述保护屏障包围所述栅极堆叠，在所述鳍片和所述保护屏障的部分上沉积第二绝缘体层，执行第一蚀刻工艺以选择性地去除所述第二绝缘体层的部分以限定空腔 其暴露鳍片的源极和漏极区域的部分，而不明显地去除保护屏障，以及在空腔中沉积导电材料。
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公开(公告)号：US20170199139A1
公开(公告)日：2017-07-13
申请号：US14992319
申请日：2016-01-11
CPC分类号： G01N27/02 , G01B11/0625 , G01B11/0683 , G01N21/211 , G01N21/25 , G01N21/27 , G01N21/8422 , G01N21/9501 , G01N2021/3568 , G01N2021/4126 , G01N2201/129
摘要： In an embodiment, a method comprises fitting a spectroscopic data of a layer in a layered structure to a dielectric function having a real part and an imaginary part; confirming that the dielectric function is physically possible; based on the dielectric function not being physically possible, repeating the fitting the spectroscopic data, or, based on the dielectric function being physically possible, defining an n degree polynomial to the dielectric function; determining a second derivative and a third derivative of the n degree polynomial; equating the second derivative to a first governing equation and the third derivative to a second governing equation and determining a constant of the first governing equation and the second governing equation; and based on the key governing equations, determining one or more of a band gap, a thickness, and a concentration of the layer.
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7.发明授权Structure and method for highly strained germanium channel fins for high mobility pFINFETs 有权用于高迁移率pFINFET的高应变锗通道翅片的结构和方法公开(公告)号：US09502420B1
公开(公告)日：2016-11-22
申请号：US14975721
申请日：2015-12-19
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/10
CPC分类号： H01L27/0924 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/823431 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L27/0922 , H01L29/1054 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method is provided that includes providing a material stack of, from bottom to top, a relaxed and n-type doped silicon germanium alloy layer and a relaxed silicon germanium alloy layer, each layer having a uniform germanium content, on a surface of a relaxed and graded silicon germanium alloy buffer layer that is located within a pFET device region of a semiconductor substrate. Next, the relaxed silicon germanium alloy layer is patterned to provide at least one relaxed silicon germanium alloy fin having the uniform germanium content on the relaxed and n-type doped silicon germanium alloy layer. A strained germanium layer is then formed surrounding the at least one relaxed silicon germanium alloy fin. A portion of the strained germanium layer and the at least one relaxed silicon germanium alloy fin can be used as composited channel material for fabricating a pFinFET device.
摘要翻译： 提供了一种方法，其包括从放置的放置的表面提供从底部到顶部放松和n型掺杂的硅锗合金层和松弛的硅锗合金层的材料堆叠，每个层具有均匀的锗含量 以及位于半导体衬底的pFET器件区域内的分级硅锗合金缓冲层。 接下来，将松弛的硅锗合金层图案化以在松弛和n型掺杂的硅锗合金层上提供至少一个具有均匀锗含量的松弛硅锗合金翅片。 然后围绕至少一个松弛的硅锗合金翅片形成应变的锗层。 应变锗层和至少一个松弛硅锗合金翅片的一部分可以用作用于制造pFinFET器件的复合通道材料。
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8.发明申请公开(公告)号：US20160336345A1
公开(公告)日：2016-11-17
申请号：US15220608
申请日：2016-07-27
IPC分类号： H01L27/12 , H01L29/06 , H01L29/161 , H01L29/78 , H01L21/84 , H01L21/8234 , H01L21/02 , H01L29/10 , H01L29/04
CPC分类号： H01L27/1203 , H01L21/02532 , H01L21/02609 , H01L21/7624 , H01L21/76264 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L27/1218 , H01L27/1229 , H01L29/045 , H01L29/0649 , H01L29/1033 , H01L29/161 , H01L29/7838 , H01L29/78603 , H01L29/78687
摘要： Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.
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公开(公告)号：US20150311127A1
公开(公告)日：2015-10-29
申请号：US14739627
申请日：2015-06-15
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/225 , H01L29/40 , H01L29/423
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。
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公开(公告)号：US10573565B2
公开(公告)日：2020-02-25
申请号：US16273779
申请日：2019-02-12
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/51 , H01L29/78 , H01L21/84 , H01L29/49 , H01L29/66 , H01L29/786
摘要： An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
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