公开(公告)号：US20170207070A1

公开(公告)日：2017-07-20

申请号：US15479597

申请日：2017-04-05

Applicant: Lam Research Corporation

Inventor： Yassine Kabouzi ,  Jorge Luque ,  Andrew D. Bailey, III ,  Mehmet Derya Tetiker ,  Ramkumar Subramanian ,  Yoko Yamaguchi

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01J37/32963 ,  H01J37/32082 ,  H01J37/32137 ,  H01J37/32183 ,  H01J37/32532 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67253 ,  H01L22/26

Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.

公开(公告)号：US20170176983A1

公开(公告)日：2017-06-22

申请号：US14972969

申请日：2015-12-17

Applicant: Lam Research Corporation

Inventor： Mehmet Derya Tetiker ,  Saravanapriyan Sriraman ,  Andrew D. Bailey, III ,  Juline Shoeb ,  Alex Paterson ,  Richard A. Gottscho

IPC: G05B19/418

CPC classification number: G05B19/4188 ,  G05B17/02 ,  G05B2219/45031 ,  G05B2219/45212

Abstract: Disclosed are methods of optimizing a computerized model which relates etched feature profile on a semiconductor device to a set of independent input parameters via the use of a plurality of model parameters. The optimization methods may include modifying the model parameters so that an etch profile generated with the model is such that it reduces a metric indicative of the combined differences between experimental etch profiles resulting from experimental etch processes performed using different sets of values for sets of independent input parameters and computed etch profiles generated from the model and corresponding to the experimental etch profiles. Said metric may be calculated by projecting computed and corresponding experimental etch profiles onto a reduced-dimensional subspace used to calculate a difference between the profiles. Also disclosed herein are systems employing such optimized models, as well as methods of using such models to approximately determine the profile of an etched feature.

公开(公告)号：US20170084503A1

公开(公告)日：2017-03-23

申请号：US14862983

申请日：2015-09-23

Applicant: Lam Research Corporation

Inventor： Yassine Kabouzi ,  Luc Albarede ,  Andrew D. Bailey, III ,  Jorge Luque ,  Seonkyung Lee ,  Thorsten Lill

IPC: H01L21/66 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L22/26 ,  H01J37/32981 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/32137 ,  H01L28/00

Abstract: A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed, wherein the dry processing creates at least one gas byproduct. A concentration of the at least one gas byproduct is measured. The concentration of the at least one gas byproduct is used to determine processing rate of the substrate.

公开(公告)号：US20160314943A1

公开(公告)日：2016-10-27

申请号：US14694356

申请日：2015-04-23

Applicant: Lam Research Corporation

Inventor： Luc Albarede ,  Yassine Kabouzi ,  Jorge Luque ,  Andrew D. Bailey, III

IPC: H01J37/32

CPC classification number: H01J37/32963 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32449 ,  H01J37/32972 ,  H01J37/32981 ,  H01J37/3299 ,  H01J2237/334

Abstract: A substrate etching system includes an etching control module, a filtering module, and an endpoint module. The etching control module selectively begins plasma etching of a substrate within an etching chamber. The filtering module, during the plasma etching of the substrate: receives a signal including endpoint information; decomposes the signal using empirical mode decomposition (EMD); and generates a filtered signal based on results of the EMD. The endpoint module indicates when an endpoint of the plasma etching of the substrate has been reached based on the filtered signal. The etching control module ends the plasma etching of the substrate in response to the indication that the endpoint of the plasma etching of the substrate has been reached.

Abstract translation: 衬底蚀刻系统包括蚀刻控制模块，过滤模块和端点模块。 蚀刻控制模块选择性地开始蚀刻室内的衬底的等离子体蚀刻。 过滤模块在衬底的等离子体蚀刻期间：接收包括端点信息的信号; 使用经验模式分解（EMD）分解信号; 并根据EMD的结果生成滤波信号。 端点模块基于滤波信号指示何时已经到达基板的等离子体蚀刻的端点。 响应于已经达到衬底的等离子体蚀刻的终点的指示，蚀刻控制模块结束衬底的等离子体蚀刻。

公开(公告)号：US09418859B2

公开(公告)日：2016-08-16

申请号：US14676711

申请日：2015-04-01

Applicant: Lam Research Corporation

Inventor： Eric A. Hudson ,  Andrew D. Bailey, III ,  Rajinder Dhindsa

IPC: H01L21/3065 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/3065 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32192 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32458 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67069

Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.

公开(公告)号：US20160111309A1

公开(公告)日：2016-04-21

申请号：US14517623

申请日：2014-10-17

Applicant: Lam Research Corporation

Inventor： Thorsten Lill ,  Vahid Vahedi ,  Candi Kristoffersen ,  Andrew D. Bailey, III ,  Meihua Shen ,  Rangesh Raghavan ,  Gary Bultman

IPC: H01L21/677 ,  H01L21/68 ,  H01L21/683 ,  H01L21/673

CPC classification number: H01L21/67745 ,  H01L21/67766

Abstract: An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front wall, a back wall, first and second side walls, a top wall, and a bottom wall. The first side wall and the second side wall include two or more wafer load ports wherein each wafer load port is adapted to receive a FOUP. The front wall includes wafer ports configured to attach to respective load locks operable to allow a wafer to be transferred to a front wall cluster processing tool. The back wall includes a wafer port adapted to be in operational relationship with a back wall cluster processing tool. A robot in the EFEM enclosure is operable to transfer wafers through the wafer load ports, the first front wall wafer port, the second front wall wafer port, and the back wall wafer port.

Abstract translation: 用于将晶片转移到晶片处理模块和从晶片处理模块传送晶片的EFEM包括具有由前壁，后壁，第一和第二侧壁，顶壁和底壁限定的受控环境的外壳。 第一侧壁和第二侧壁包括两个或更多个晶片负载端口，其中每个晶片负载端口适于接收FOUP。 前壁包括被配置为附接到可操作以允许将晶片转移到前壁群集处理工具的相应负载锁的晶片端口。 后壁包括适于与后壁群集处理工具处于操作关系的晶片端口。 EFEM外壳中的机器人可操作以通过晶片加载端口，第一前壁晶片端口，第二前壁晶圆端口和后壁晶圆端口传送晶片。

公开(公告)号：US20160111261A1

公开(公告)日：2016-04-21

申请号：US14523770

申请日：2014-10-24

Applicant: Lam Research Corporation

Inventor： Yassine Kabouzi ,  Jorge Luque ,  Andrew D. Bailey, III ,  Mehmet Derya Tetiker ,  Ramkumar Subramanian ,  Yoko Yamaguchi

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32963 ,  H01J37/32082 ,  H01J37/32137 ,  H01J37/32183 ,  H01J37/32532 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67253 ,  H01L22/26

Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.

Abstract translation: 在多模脉冲过程中识别所选择的过程点的系统和方法包括对等离子体处理室中的所选择的晶片应用多模式脉冲处理，多模式脉冲处理包括多个周期，每个周期 包括多个不同阶段中的至少一个。 在所选晶片的多个周期期间，为所选择的至少一个相位收集至少一个过程输出变量。 可以使用所收集的至少一个过程输出变量的信封和/或模板来识别所选择的过程点。 可以将先前阶段的收集的过程输出变量的第一轨迹与选定阶段的过程输出变量的第二轨迹进行比较。 可以计算第二轨迹的多变量分析统计量，并用于识别所选择的过程点。

公开(公告)号：US09281166B2

公开(公告)日：2016-03-08

申请号：US14189978

申请日：2014-02-25

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Andrew D. Bailey, III

IPC: C23C16/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract translation: 处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。 第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。 第二电极配置有与晶片支撑件相对的中心区域。 第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。 第二电接地环与中心区电气隔离。 环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。 提供DC控制电路以向DC偏置环施加DC电压。

公开(公告)号：US20150311129A1

公开(公告)日：2015-10-29

申请号：US14265275

申请日：2014-04-29

Applicant: Lam Research Corporation

Inventor： Alan Jeffrey Miller ,  Evelio Sevillano ,  Jorge Luque ,  Andrew D. Bailey, III ,  Qing Xu

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L22/26 ,  H01L21/3065 ,  H01L21/67253 ,  H01L21/76898 ,  H01L22/12

Abstract: Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior region with a wafer receiving mechanism and a viewport disposed on a sidewall of the plasma processing chamber providing visual access from the exterior to the wafer received on the wafer receiving mechanism. A camera is mounted to the viewport of the plasma processing chamber on the exterior and coupled to an image processor. The image processor includes pattern recognition logic to match images of emerging pattern captured and transmitted by the camera, to a reference pattern and to generate signal defining an endpoint when a match is detected. A system process controller coupled to the image processor and the plasma processing chamber receives the signal from the image processor and adjusts controls of one or more resources to stop the etching operation.

Abstract translation: 用于处理半导体晶片的系统和方法包括等离子体处理室。 等离子体处理室包括外部，具有晶片接收机构的内部区域和设置在等离子体处理室的侧壁上的视口，其提供从外部到晶片接收机构上接收的晶片的视觉访问。 照相机安装在外部的等离子体处理室的视口上并耦合到图像处理器。 图像处理器包括图案识别逻辑，以将由相机捕获和发射的新兴图案的图像与参考图案相匹配，并且当检测到匹配时产生定义端点的信号。 耦合到图像处理器和等离子体处理室的系统处理控制器接收来自图像处理器的信号，并且调整一个或多个资源的控制以停止蚀刻操作。

公开(公告)号：US08940098B2

公开(公告)日：2015-01-27

申请号：US13933515

申请日：2013-07-02

Applicant: Lam Research Corporation

Inventor： Greg Sexton ,  Andrew D. Bailey, III ,  Alan Schoepp

IPC: B08B5/00 ,  H01L21/02 ,  B08B7/00 ,  H01J37/32

CPC classification number: H01L21/02087 ,  B08B7/0035 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32706 ,  Y10S134/902

Abstract: A plasma etch processing chamber configured to clean a bevel edge of a substrate is provided. The chamber includes a bottom edge electrode and a top edge electrode defined over the bottom edge electrode. The top edge electrode and the bottom edge electrode are configured to generate a cleaning plasma to clean the bevel edge of the substrate. The chamber includes a gas feed defined through a top surface of the processing chamber. The gas feed introduces a processing gas for striking the cleaning plasma at a location in the processing chamber that is between an axis of the substrate and the top edge electrode. A pump out port is defined through the top surface of the chamber and the pump out port located along a center axis of the substrate. A method for cleaning a bevel edge of a substrate is also provided.

Abstract translation: 提供了一种构造成清洁衬底的斜边缘的等离子体蚀刻处理室。 该室包括底边缘电极和限定在底部边缘电极上的顶部边缘电极。 顶边电极和底边电极被配置为产生清洁等离子体以清洁基板的斜边缘。 该室包括通过处理室的顶表面限定的气体进料。 气体进料引入处理气体，用于在位于基板的轴线和顶部边缘电极之间的处理室中的位置处冲击清洁等离子体。 泵出口通过腔室的顶表面和沿着衬底的中心轴线定位的泵出口来限定。 还提供了一种用于清洁基板的斜边缘的方法。