摘要:
A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.
摘要:
A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.
摘要:
An apparatus for nano lithography includes a mask having a pattern formed thereon and a pneumatic pressure driving source for applying a pneumatic pressure to at least one of a surface of the mask and a surface of a workpiece, thereby to uniformly transfer the pattern from the mask to the workpiece.
摘要:
An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.
摘要:
A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.
摘要:
A system for imprint lithography, which includes a substrate, a patterned mask, an imprint applying unit that imprints, via the patterned mask, a pattern into a resist layer on the substrate, and an overlay device that overlays a cladding layer over the substrate.
摘要:
Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.
摘要:
The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.
摘要:
A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要:
Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.