公开(公告)号：US06525381B1

公开(公告)日：2003-02-25

申请号：US09541127

申请日：2000-03-31

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2976

CPC分类号： H01L29/66772 ,  H01L29/41733 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US06492249B2

公开(公告)日：2002-12-10

申请号：US09304129

申请日：1999-05-03

申请人： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

发明人： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/31658 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

摘要翻译： 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高K栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06451693B1

公开(公告)日：2002-09-17

申请号：US09679370

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

IPC分类号： H01L2144

CPC分类号： H01L29/66613 ,  H01L21/28518 ,  H01L29/66507

摘要： A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.

摘要翻译： 形成硅化物栅极接触，其比在源极/漏极区域和浅结延伸部分上形成的硅化物触点相对更厚。 首先沉积金属层以在多晶硅栅极和源极/漏极延伸区域上形成硅化物。 从延伸区域去除硅化物，形成浅结，并且多晶硅栅极上保留一层硅化物。 第二金属沉积步骤和硅化步骤在源极/漏极区域和多晶硅栅极之上形成硅化物接触。 所得到的硅化物栅极接触比源极/漏极区上的所得硅化物接触厚。

公开(公告)号：US06436840B1

公开(公告)日：2002-08-20

申请号：US09691188

申请日：2000-10-19

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。

公开(公告)号：US06420770B1

公开(公告)日：2002-07-16

申请号：US09882244

申请日：2001-06-15

申请人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

发明人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC分类号： H01L2900

CPC分类号： H01L29/665 ,  H01L21/76224

摘要： STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

摘要翻译： 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。

公开(公告)号：US06239452B1

公开(公告)日：2001-05-29

申请号：US09320682

申请日：1999-05-27

申请人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

发明人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

IPC分类号： H01L2184

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

摘要： A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

摘要翻译： 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

公开(公告)号：US06218245B1

公开(公告)日：2001-04-17

申请号：US09198654

申请日：1998-11-24

申请人： Qi Xiang ,  Xiao-Yu Li

发明人： Qi Xiang ,  Xiao-Yu Li

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11558 ,  Y10S438/91

摘要： A method for fabricating a high-density and high-reliability EEPROM device includes providing a semiconductor substrate having both an EEPROM cell region, and a peripheral MOS transistor region. A gate oxide layer is formed to overlie the peripheral MOS transistor region and the EEPROM cell region. A tunnel oxide region is formed to overlie a portion of the EEPROM cell region. Then, a polycrystalline silicon layer is formed to overlie both the gate oxide layer and the tunnel oxide region. A deuterium annealing process is then carried out to anneal the gate oxide layer and the tunnel oxide region. The polycrystalline silicon layer is patterned to form numerous gate electrodes including gate electrodes for peripheral transistors, floating-gate transistors, and read and write transistors in the EEPROM cell.

摘要翻译： 一种用于制造高密度和高可靠性EEPROM器件的方法包括提供具有EEPROM单元区域和外围MOS晶体管区域的半导体衬底。 形成栅极氧化层以覆盖外围MOS晶体管区域和EEPROM单元区域。 形成隧道氧化物区域以覆盖EEPROM单元区域的一部分。 然后，形成多晶硅层以覆盖栅极氧化物层和隧道氧化物区域两者。 然后进行氘退火处理以退火栅极氧化物层和隧道氧化物区域。 图案化多晶硅层以形成多个栅电极，其包括用于外围晶体管的栅电极，浮栅晶体管以及EEPROM单元中的读写晶体管。

公开(公告)号：US6087696A

公开(公告)日：2000-07-11

申请号：US86437

申请日：1998-05-28

申请人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

发明人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/513 ,  H01L29/517 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518

摘要： An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.

摘要翻译： 提供了改进的EEPROM单元结构及其制造方法，以便改善数据保留。 EEPROM单元包括由薄的隧道氧化物层和高k电介质层构成的叠层电介质结构，用作隧道电介质势垒，以便抑制漏电流。

公开(公告)号：US08804407B1

公开(公告)日：2014-08-12

申请号：US13181219

申请日：2011-07-12

申请人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

发明人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H03K2217/0054

摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

摘要翻译： 描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。 在一个实现中，PMOS晶体管具有负阈值电压。 在一个实现中，存储单元包括厚的氧化物晶体管。

公开(公告)号：US08735983B2

公开(公告)日：2014-05-27

申请号：US12324791

申请日：2008-11-26

申请人： Jun Liu ,  Albert Ratnakumar ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

发明人： Jun Liu ,  Albert Ratnakumar ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L21/823842 ,  H01L21/28 ,  H01L21/28061 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7833

摘要： Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

摘要翻译： 提供了金属氧化物半导体晶体管。 可以在半导体衬底上形成金属氧化物半导体晶体管。 源极和漏极区可以形成在衬底中。 可以在源极和漏极区域之间形成诸如高K电介质的栅极绝缘体。 栅极可以由多个栅极导体形成。 栅极导体可以是具有不同功函数的金属。 栅极导体中的第一个可以形成与电介质间隔物相邻的一对边缘栅极导体。 边缘栅极导体之间​​的开口可以用第二栅极导体填充以形成中心栅极导体。 可以在制造金属氧化物半导体晶体管中使用自对准栅极形成工艺。