公开(公告)号：US20240145400A1

公开(公告)日：2024-05-02

申请号：US18227357

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhyuk Kim ,  Jeongyong Sung ,  Joongshik Shin ,  Jeehoon Han

IPC: H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H01L2223/54426

Abstract: A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

公开(公告)号：US11854975B2

公开(公告)日：2023-12-26

申请号：US17459406

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US11792994B2

公开(公告)日：2023-10-17

申请号：US17659990

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Jongseon Ahn ,  Jeehoon Han

IPC: H10B43/35 ,  H01L29/49 ,  H01L21/28 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L21/28052 ,  H01L29/4933 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

公开(公告)号：US11791262B2

公开(公告)日：2023-10-17

申请号：US17475128

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L29/423 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L29/42356 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US20230062069A1

公开(公告)日：2023-03-02

申请号：US17860800

申请日：2022-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhwan Son ,  Hyeongjin Kim ,  Seungjun Shin ,  Joongshik Shin ,  Minsoo Shin ,  Jeehoon Han

IPC: G11C16/04 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a lower stepped connection part at a first vertical level on a substrate, an upper stepped connection part at a second vertical level higher than the first vertical level on the substrate, a lower insulating block contacting each of the plurality of lower conductive pad parts at the first vertical level, an upper insulating block contacting each of the plurality of upper conductive pad parts at the second vertical level, an intermediate insulating film between the lower insulating block and the upper insulating block at a third vertical level between the first and second vertical levels, and a first plug structure extending into the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction, wherein a width of the first plug structure in the horizontal direction is greatest at the third vertical level.

公开(公告)号：US20230028532A1

公开(公告)日：2023-01-26

申请号：US17703130

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanamori Kohji ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.

公开(公告)号：US20220359563A1

公开(公告)日：2022-11-10

申请号：US17651633

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji Noh ,  Jung-Hwan Park ,  Kwangyoung Jung ,  Hyojoon Ryu ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

Abstract: Provided are three-dimensional semiconductor memory devices and electronic systems including the same. The device includes a substrate, stack structures each including interlayer dielectric layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, vertical channel structures which penetrate the stack structures, and a separation structure, which extends in a first direction across between the stack structures. The separation structure includes first parts each having a pillar shape, which extend in a third direction perpendicular to a top surface of the substrate, and second parts, which extend between the interlayer dielectric layers from sidewalls of the first parts and which connect the first parts to each other in the first direction. The separation structure is spaced apart from the vertical channel structures in a second direction which intersects the first direction.

公开(公告)号：US20220344244A1

公开(公告)日：2022-10-27

申请号：US17571874

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojoon Ryu ,  Bongyong Lee ,  Heesuk Kim ,  Junhee Lim ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.

公开(公告)号：US20220310652A1

公开(公告)日：2022-09-29

申请号：US17838644

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L29/417 ,  H01L29/423 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11597 ,  H01L27/11551

Abstract: Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

公开(公告)号：US11444098B2

公开(公告)日：2022-09-13

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan Son ,  Seungwon Lee ,  Seogoo Kang ,  Juyoung Lim ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.