公开(公告)号：US20190228967A1

公开(公告)日：2019-07-25

申请号：US16337206

申请日：2017-09-21

Applicant: Soitec

Inventor： David Sotta ,  Jean-Marc Bethoux ,  Oleg Kononchuk

IPC: H01L21/02

Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.

公开(公告)号：US20190007024A1

公开(公告)日：2019-01-03

申请号：US16064419

申请日：2016-12-21

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H01L27/20 ,  H01L41/047

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20170331501A1

公开(公告)日：2017-11-16

申请号：US15531976

申请日：2015-09-17

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Didier Landru ,  Christophe Figuet

IPC: H04B1/03 ,  H01M4/66 ,  H01L21/02 ,  H01L21/762 ,  H01L41/047 ,  H01L21/28

CPC classification number: H04B1/03 ,  H01L21/02167 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28282 ,  H01L21/76254 ,  H01L21/76297 ,  H01L41/0477 ,  H01M4/663

Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower 10,000 ohm·cm over a temperature range extending from −20° C. to 120° C.

公开(公告)号：US09679799B2

公开(公告)日：2017-06-13

申请号：US14441473

申请日：2013-09-25

Applicant: Soitec

Inventor： Christophe Gourdel ,  Oleg Kononchuk

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L21/7624 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/84

Abstract: The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment step is designed to partially dissolve the silicon dioxide layer, the heat treatment step being carried out in a non-oxidizing atmosphere and the pressure of the non-oxidizing atmosphere being lower than 0.1 bar.

公开(公告)号：US20170062236A1

公开(公告)日：2017-03-02

申请号：US15350290

申请日：2016-11-14

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk

IPC: H01L21/322 ,  H01L21/762

CPC classification number: H01L21/3225 ,  H01L21/3226 ,  H01L21/324 ,  H01L21/7624

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Abstract translation: 本公开涉及一种将二氧化硅层溶解在结构中的方法，包括从其后表面到其前表面的支撑衬底，二氧化硅层和半导体层，该溶解方法在炉中实施 其中结构支撑在载体上，溶解方法导致二氧化硅层中包含的氧原子扩散通过半导体层并产生挥发性产物，并且该炉包括适于与挥发性产物反应的阱，以便 降低与至少一个结构的前表面平行的挥发性产物的浓度梯度。

公开(公告)号：US09514960B2

公开(公告)日：2016-12-06

申请号：US14779477

申请日：2014-03-03

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk

IPC: H01L21/322 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L21/3225 ,  H01L21/3226 ,  H01L21/324 ,  H01L21/7624

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Abstract translation: 本公开涉及一种将二氧化硅层溶解在结构中的方法，包括从其后表面到其前表面的支撑衬底，二氧化硅层和半导体层，该溶解方法在炉中实施 其中结构支撑在载体上，溶解方法导致二氧化硅层中包含的氧原子扩散通过半导体层并产生挥发性产物，并且该炉包括适于与挥发性产物反应的阱，以便 降低与至少一个结构的前表面平行的挥发性产物的浓度梯度。

公开(公告)号：US20150300809A1

公开(公告)日：2015-10-22

申请号：US14442081

申请日：2013-09-19

Applicant: SOITEC ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Oleg Kononchuk ,  Didier Dutartre

IPC: G01B11/06 ,  G02B21/36 ,  H01L21/66

CPC classification number: G01B11/06 ,  G01B11/0633 ,  G01B11/30 ,  G02B21/361 ,  H01L22/12

Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to the given thickness difference, the thicknesses of the other layers being for their part identical in the two multilayer structures. The invention also relates to a measuring system implementing the method.

Abstract translation: 本发明涉及一种用于测量多层半导体结构的层中的厚度变化的方法，其特征在于，其包括：经由图像采集系统获取所述结构的表面的至少一个图像，所述图像通过反射 来自结构表面的几乎单色的光通量; 并且处理所述至少一个获取的图像，以便根据从表面反射的光的强度的变化来确定被测量层的厚度的变化，并且选择几乎单色光束的波长 对应于除了必须测量其厚度变化的层之外的结构层的反射率的最小灵敏度，层的反射率的灵敏度等于：反射率之间的差异 的两层多层结构，其中所述层具有给定的厚度差; 对于给定的厚度差，其他层的厚度在两个多层结构中的部分相同。 本发明还涉及实现该方法的测量系统。

公开(公告)号：US09136113B2

公开(公告)日：2015-09-15

申请号：US14044846

申请日：2013-10-02

Applicant: SOITEC

Inventor： Didier Landru ,  Fabrice Gritti ,  Eric Guiot ,  Oleg Kononchuk ,  Christelle Veytizou

IPC: H01L21/461 ,  H01L21/02 ,  H01L21/316 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/3247 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/31662 ,  H01L21/7624

Abstract: A process for avoiding formation of an Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.

Abstract translation: 在绝缘体上半导体结构的溶解处理中避免形成Si-SiO 2 -H 2环境的方法，其包括载体衬底，氧化物层，半导体材料的薄层和外围环，其中氧化物 层暴露。 该方法包括通过进行蠕变热处理将至少外围环的暴露的氧化物层与半导体材料封装起来; 并进行氧化物溶解处理以减少氧化物层的厚度的一部分。 在该方法中，封装氧化物层的半导体材料的氧化物溶解前的厚度为要溶解的氧化物的至少两倍，因此避免在外围环上形成Si-SiO 2 -H 2环境， 否则会暴露氧化层。

公开(公告)号：US20250125140A1

公开(公告)日：2025-04-17

申请号：US18834122

申请日：2023-01-27

Applicant: Soitec

Inventor： Andrea Quintero-Colmenares ,  Frédéric Allibert ,  Alexis Drouin ,  Séverin Rouchier ,  Walter Schwarzenbach ,  Hugo Biard ,  Loïc Kabelaan ,  Oleg Kononchuk ,  Sidoine Odoul ,  Jérémy Roi

IPC: H01L21/02 ,  H01L21/324

Abstract: A method of manufacturing a polycrystalline silicon carbide wafer includes the following stages: heat treatment of a polycrystalline silicon carbide slab; thinning of the polycrystalline silicon carbide slab, the thinning comprising a correction, by withdrawal of material from the polycrystalline silicon carbide slab, of a deformation brought about by the heat treatment.

公开(公告)号：US20250022747A1

公开(公告)日：2025-01-16

申请号：US18901953

申请日：2024-09-30

Applicant: Soitec

Inventor： Fabrice Letertre ,  Oleg Kononchuk

IPC: H01L21/762 ,  B32B7/12 ,  B32B9/04 ,  C30B29/68 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02 ,  H01L21/18 ,  H01L27/12 ,  H01L33/00

Abstract: A method for fabricating a structure comprises preparing a first pseudo-substrate, and in-depth weakening the first pseudo-substrate by ion implantation at a certain depth in the first pseudo-substrate. The first pseudo-substrate is prepared by providing a single crystal substrate comprising a piezoelectric material; forming an oxide layer on a surface of the single crystal substrate; and transferring a piezoelectric layer of the single crystal substrate adjacent the oxide layer to a handle substrate to form the first pseudo-substrate. The method further comprises bonding the first pseudo-substrate to a substrate to provide an assembly, and separating the assembly at the ion-implanted depth of the first pseudo-substrate to form the structure and a second pseudo-substrate. The structure comprises at least a portion of the piezoelectric layer of the single crystal substrate on the substrate.