公开(公告)号：US20130069161A1

公开(公告)日：2013-03-21

申请号：US13233064

申请日：2011-09-15

申请人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L29/42372 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/78

摘要： Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.

摘要翻译： 在栅极上利用选择性地形成和至少部分氧化的金属盖形成集成电路结构的方法以及相关联的结构。 在一个实施例中，一种方法包括提供包括具有金属栅极的晶体管的前体结构; 在所述金属栅极的暴露部分上形成蚀刻停止层; 至少部分氧化所述蚀刻停止层; 以及在所述至少部分氧化的蚀刻停止层上形成电介质层。

公开(公告)号：US20130065376A1

公开(公告)日：2013-03-14

申请号：US13616882

申请日：2012-09-14

申请人： David Vaclav Horak ,  Shom Ponoth ,  Hosadurga Shobha ,  Chih-Chao Yang

发明人： David Vaclav Horak ,  Shom Ponoth ,  Hosadurga Shobha ,  Chih-Chao Yang

IPC分类号： H01L21/02

CPC分类号： H01L28/88 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/3212

摘要： A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.

摘要翻译： 公开了一种半导体电容器及其制造方法。 使用非线性氮化物层来增加电容器板的表面积，导致增加的电容，而不增加用于电容器的芯片面积。

公开(公告)号：US20120326237A1

公开(公告)日：2012-12-27

申请号：US13169081

申请日：2011-06-27

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L29/772

CPC分类号： H01L21/76895 ,  H01L21/823475 ,  H04L45/58 ,  H04L49/15 ,  H04L49/45

摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.

摘要翻译： 本发明的实施例提供一种结构。 该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触点 晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。

公开(公告)号：US08232204B1

公开(公告)日：2012-07-31

申请号：US13171527

申请日：2011-06-29

申请人： David V. Horak ,  Charles W. Koburger, III ,  Steven J. Holmes ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Charles W. Koburger, III ,  Steven J. Holmes ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/78

摘要： Embodiments of the present invention provide a method of forming borderless contact for transistor. The method may include forming a gate of a transistor, on top of a substrate, and spacers adjacent to sidewalls of the gate; forming a sacrificial layer surrounding the gate; causing the sacrificial layer to expand in height to become higher than the gate, the expanded sacrificial layer covering at most a portion of a top surface of the spacers and thereby leaving an opening on top of the gate surrounded by the spacers; filling the opening with a dielectric cap layer; replacing the expanded sacrificial layer with a dielectric layer; and forming a conductive stud contacting source/drain of the transistor, the conductive stud being isolated from the gate by the dielectric cap layer.

摘要翻译： 本发明的实施例提供一种形成晶体管的无边界接触的方法。 该方法可以包括在衬底的顶部上形成晶体管的栅极和邻近栅极的侧壁的间隔物; 形成围绕所述栅极的牺牲层; 导致牺牲层在高度上膨胀以变得高于栅极，所述扩展的牺牲层覆盖所述间隔物的顶表面的至多一部分，从而在由所述间隔物包围的所述栅极的顶部上留下开口; 用介电盖层填充开口; 用介电层代替扩展的牺牲层; 并且形成与晶体管的导电柱接触的源极/漏极，导电柱通过电介质盖层与栅极隔离。

公开(公告)号：US20120153503A1

公开(公告)日：2012-06-21

申请号：US13407933

申请日：2012-02-29

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

公开(公告)号：US20110101538A1

公开(公告)日：2011-05-05

申请号：US12610624

申请日：2009-11-02

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 还提供了由此制成的半导体结构。

公开(公告)号：US20110084403A1

公开(公告)日：2011-04-14

申请号：US12575980

申请日：2009-10-08

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05547 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/08121 ,  H01L2224/80001 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80359 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/82

摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

摘要翻译： 将两个基材放在一起并放置在电镀浴中。 在一个实施例中，将导电材料电镀在存在于第一金属焊盘和第二金属焊盘之间的界面处的微观空腔中，以形成粘附到第一金属焊盘的表面的至少一个界面电镀金属衬垫部分， 第二个金属垫。 在另一个实施例中，至少一个金属焊盘相对于电介质表面在被聚集之前是凹进的。 将两个基板放置在电镀槽中，并且将导电材料镀在第一金属焊盘和第二金属焊盘之间的空腔中，以形成附着在第一金属焊盘的表面上的连续的电镀金属衬垫层， 第二个金属垫。

公开(公告)号：US20090278258A1

公开(公告)日：2009-11-12

申请号：US12115944

申请日：2008-05-06

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53295 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.

摘要翻译： 提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。 电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个 多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征 。 本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在 第一电介质盖58。

公开(公告)号：US20090072409A1

公开(公告)日：2009-03-19

申请号：US11855211

申请日：2007-09-14

申请人： Satya V. Nitta ,  Shom Ponoth

发明人： Satya V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/52

CPC分类号： H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

摘要翻译： 双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。 沟槽和导电金属柱和通孔具有共同的轴线。 这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。 在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及 在通孔中向下延伸距离线下方约1埃至通孔的整个深度。 在另一方面，制品包括封盖的双镶嵌结构。

公开(公告)号：US20090008361A1

公开(公告)日：2009-01-08

申请号：US11774041

申请日：2007-07-06

申请人： John A. Fitzsimmons ,  David L. Rath ,  Shom Ponoth ,  Michael Beck

发明人： John A. Fitzsimmons ,  David L. Rath ,  Shom Ponoth ,  Michael Beck

IPC分类号： H01B13/00 ,  B05D5/12 ,  C09K13/00 ,  C09K13/08

CPC分类号： C23G1/103 ,  H01L21/02063

摘要： A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

摘要翻译： 微电子结构中可用于清洗含金属导体层（例如含铜导电体层）的组合物包括酸水溶液以及氧化剂材料和含水酸性物质中的钝化材料。 组合物不包括研磨材料。 所述组合物特别可用于从含铜导体层和邻接的介电层清洁残留物，所述相邻介电层提供用于在微电子结构内进入含铜导体层的孔。