公开(公告)号：US11017864B2

公开(公告)日：2021-05-25

申请号：US16453211

申请日：2019-06-26

Applicant: Seagate Technology LLC

Inventor： Kurt Walter Getreuer ,  Darshana H. Mehta ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G01K1/14

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.

公开(公告)号：US10956064B2

公开(公告)日：2021-03-23

申请号：US16456809

申请日：2019-06-28

Applicant: Seagate Technology LLC

Inventor： Darshana H. Mehta ,  Kurt Walter Getreuer ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.

公开(公告)号：US10592134B1

公开(公告)日：2020-03-17

申请号：US15859689

申请日：2018-01-01

Applicant: Seagate Technology LLC

Inventor： Ryan James Goss ,  Antoine Khoueir ,  Ara Patapoutian

IPC: G06F3/06 ,  G11C16/34

Abstract: Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.

公开(公告)号：US10095568B2

公开(公告)日：2018-10-09

申请号：US15498595

申请日：2017-04-27

Applicant: Seagate Technology, LLC

Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

IPC: G11C16/04 ,  G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26

Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

公开(公告)号：US09881678B2

公开(公告)日：2018-01-30

申请号：US15411040

申请日：2017-01-20

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Young Pil Kim ,  Antoine Khoueir ,  Namoh Hwang

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  G11C29/50 ,  G11C29/00 ,  G11C29/02 ,  G11C16/34 ,  G11C29/28 ,  G11C29/42 ,  G11C29/26 ,  G11C29/12

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/025 ,  G11C29/026 ,  G11C29/26 ,  G11C29/28 ,  G11C29/42 ,  G11C29/50012 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

公开(公告)号：US09786677B1

公开(公告)日：2017-10-10

申请号：US14552191

申请日：2014-11-24

Applicant: Seagate Technology LLC

Inventor： Antoine Khoueir ,  Frank R Dropps

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/792 ,  H01L21/762 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/76224 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/7883 ,  H01L29/7926

Abstract: A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed.

公开(公告)号：US09727459B2

公开(公告)日：2017-08-08

申请号：US14466143

申请日：2014-08-22

Applicant: Seagate Technology LLC

Inventor： Antoine Khoueir ,  Ryan James Goss ,  Jon Trantham ,  Kevin Gomez ,  Frank Dropps

IPC: G06F12/06 ,  G11C7/00 ,  G06F3/06 ,  G06F12/00 ,  G11C7/10 ,  G11C16/04 ,  G11C16/26 ,  G11C15/04

CPC classification number: G06F12/06 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0638 ,  G06F2206/1014 ,  G11C7/00 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

公开(公告)号：US20150324691A1

公开(公告)日：2015-11-12

申请号：US14704124

申请日：2015-05-05

Applicant: Seagate Technology LLC

Inventor： Frank Dropps ,  Antoine Khoueir ,  Kevin Arthur Gomez ,  Jon Trantham

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A system includes a plurality of nonvolatile memory cells and a map that assigns connections between nodes of a neural network to the memory cells. Memory devices containing nonvolatile memory cells and applicable circuitry for reading and writing may operate with the map. Information stored in the memory cells can represent weights of the connections. One or more neural processors can be present and configured to implement the neural network.

Abstract translation: 系统包括多个非易失性存储器单元和将神经网络的节点之间的连接分配给存储器单元的映射。 包含非易失性存储单元的存储器件和用于读取和写入的适用电路可以与地图一起操作。 存储在存储单元中的信息可以表示连接的权重。 可以存在并配置一个或多个神经处理器来实现神经网络。

公开(公告)号：US09164832B2

公开(公告)日：2015-10-20

申请号：US13779434

申请日：2013-02-27

Applicant: Seagate Technology LLC

Inventor： Mark Allen Gaertner ,  Ryan James Goss ,  Antoine Khoueir ,  Ara Patapoutian

IPC: G11C29/00 ,  G06F11/10 ,  G11C17/16 ,  G11C13/00

CPC classification number: G06F11/1048 ,  G06F11/1008 ,  G06F11/1044 ,  G11C13/0002 ,  G11C17/165

Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.

Abstract translation: 一般来说，数据存储设备可被构造和操作至少一个控制器，该控制器被配置为在至少一个可变电阻存储器单元中识别来自预定阈值的方差，并将第一纠错码（ECC）级别升级到第二ECC级别 至少一个可变电阻存储单元。

公开(公告)号：US20150213901A1

公开(公告)日：2015-07-30

申请号：US14679654

申请日：2015-04-06

Applicant: Seagate Technology LLC

Inventor： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney V. Bowman

IPC: G11C16/14 ,  G11C11/56

CPC classification number: G11C16/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/16 ,  G11C2013/0073 ,  G11C2211/5646

Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state.

Abstract translation: 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 在一些实施例中，装置包括存储器单元阵列和双极性电荷泵。 双极性电荷泵具有正极性电压源，其向电荷存储装置施加正电压以将所选择的存储单元编程为第一编程状态;以及负极性电压源，其向电荷存储装置施加负电压 将所选择的存储器单元编程到不同的第二编程状态。