公开(公告)号：US20050178656A1

公开(公告)日：2005-08-18

申请号：US10780919

申请日：2004-02-17

申请人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

发明人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

IPC分类号： C23C14/08 ,  C23C14/32 ,  C23C14/58 ,  C23C16/00 ,  C23C16/40 ,  C23C16/56

CPC分类号： C23C14/5806 ,  C23C14/086 ,  C23C16/40 ,  C23C16/56

摘要： Methods of forming depositing a ferroelectric thin film, such as PGO, by preparing a substrate with an upper surface of silicon, silicon oxide, or a high-k material, such as hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide, depositing an indium oxide film over the substrate, and then depositing the ferroelectric film using MOCVD.

摘要翻译： 通过制备具有硅，氧化硅或高k材料如氧化铪，氧化锆，氧化铝和氧化镧的上表面的衬底来形成沉积铁电薄膜（例如PGO）的方法，沉积 在衬底上形成氧化铟膜，然后使用MOCVD沉积铁电体膜。

公开(公告)号：US20050156254A1

公开(公告)日：2005-07-21

申请号：US10761704

申请日：2004-01-21

申请人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

发明人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/26 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/26 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

摘要翻译： 提供了一种超浅表面沟道MOS晶体管及其制造方法。 该方法包括：形成CMOS源极和漏极区域以及中间阱区域; 在覆盖所述阱区域的表面上沉积表面通道; 形成覆盖表面通道的高k电介质; 并形成覆盖高k电介质的栅电极。 通常，表面通道是金属氧化物，并且可以是以下材料之一：氧化铟（In 2 O 3），ZnO，RuO，ITO或LaX-1SrXCoO 3。 在一些方面，所述方法还包括：沉积覆盖所述表面通道的占位符材料; 并且蚀刻占位符材料以形成覆盖表面通道的栅极区域。 在一个方面，高k电介质沉积在占位符材料的沉积之前。 或者，在占位符材料的蚀刻之后沉积高k电介质。

公开(公告)号：US20050136637A1

公开(公告)日：2005-06-23

申请号：US11039543

申请日：2005-01-19

申请人： Tingkai Li ,  Sheng Hsu

发明人： Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L29/78 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28291 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78391

摘要： One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2O3 film comprises: depositing an In film using a PVD process, typically with a power in the range of 200 to 300 watts; forming a film including In overlying a substrate material; simultaneously (with the formation of the In-including film) heating the substrate material, typically the substrate is heated to a temperature in the range of 20 to 200 degrees C.; following the formation of the In-including film, post-annealing, typically in an O2 atmosphere; and, in response to the post-annealing: forming an In2O3 film; and, controlling the resistivity in the In2O3 film. For example, the resistivity can be controlled in the range of 260 to 800 ohm-cm.

摘要翻译： 使用氧化铟膜（In 2 O 3 O 3），In 2 N 3 O 3的<！ - SIPO - >单晶体铁电存储器件 >膜结构，并提供相应的制造方法。 用于控制In 2 N 3 O 3膜中的电阻率的方法包括：使用PVD工艺沉积In膜，通常具有200至300瓦特的功率; 形成包括在衬底材料中的膜; 同时（形成含In膜）加热衬底材料，通常将衬底加热至20至200℃的温度范围; 在形成含In膜之后，通常在O 2气氛中进行后退火; 并且响应于后退火：形成In 2 N 3 O 3膜; 并且控制In 2 N 3 O 3膜中的电阻率。 例如，电阻率可以控制在260至800欧姆 - 厘米的范围内。

公开(公告)号：US20050070114A1

公开(公告)日：2005-03-31

申请号：US10676983

申请日：2003-09-30

申请人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

发明人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

IPC分类号： B23B39/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/461

CPC分类号： H01L21/31122 ,  H01L21/28291 ,  H01L21/2855 ,  H01L21/32051

摘要： A method of selective etching a metal oxide layer for fabrication of a ferroelectric device includes preparing a silicon substrate, including forming an oxide layer thereon; depositing a layer of metal or metal oxide thin film on the substrate; patterning and selectively etching the metal or metal oxide thin film without substantially over etching into the underlying oxide layer; depositing a layer of ferroelectric material; depositing a top electrode on the ferroelectric material; and completing the ferroelectric device.

摘要翻译： 选择性蚀刻用于制造铁电体器件的金属氧化物层的方法包括制备硅衬底，包括在其上形成氧化物层; 在衬底上沉积一层金属或金属氧化物薄膜; 图案化和选择性地蚀刻金属或金属氧化物薄膜，而基本上不会过度蚀刻到下面的氧化物层中; 沉积一层铁电材料; 在铁电材料上沉积顶部电极; 并完成铁电器件。

公开(公告)号：US20050014296A1

公开(公告)日：2005-01-20

申请号：US10621863

申请日：2003-07-16

申请人： Tingkai Li ,  Wei Pan ,  Robert Barrowcliff ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Pan ,  Robert Barrowcliff ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L21/31604 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/57 ,  H01L29/6684

摘要： A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0

摘要翻译： 在FeRAM中形成H 2钝化层的方法包括制备硅衬底; 在大马士革结构上沉积一层TiOx薄膜，其中0

公开(公告)号：US08951842B2

公开(公告)日：2015-02-10

申请号：US13349432

申请日：2012-01-12

申请人： Xiaolong Fang ,  Lifang Xu ,  Tingkai Li ,  Thomas Gehrke

发明人： Xiaolong Fang ,  Lifang Xu ,  Tingkai Li ,  Thomas Gehrke

IPC分类号： H01L33/50 ,  H01L33/48 ,  H01L21/66 ,  H01L23/544 ,  H01L33/00 ,  H01L21/78

CPC分类号： H01L33/32 ,  H01L21/78 ,  H01L22/10 ,  H01L22/32 ,  H01L22/34 ,  H01L23/544 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/48 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

摘要翻译： 公开了半导体生长衬底和用于芯片分离的相关系统和方法。 用于制造半导体器件的代表性方法包括在位于衬底材料的相邻器件生长区域之间的切割街道上形成间隔开的结构。 该方法还可以包括通过将半导体材料的第一部分添加到器件生长区域并将半导体材料的第二部分添加到该结构体来外延生长半导体材料。 该方法还可以进一步包括在器件生长区域处形成半导体器件，并且在切割街道处通过在切割街道处去除间隔开的结构和下面的衬底材料来将半导体器件彼此分离。

公开(公告)号：US20130181219A1

公开(公告)日：2013-07-18

申请号：US13349432

申请日：2012-01-12

申请人： Xiaolong Fang ,  Lifang Xu ,  Tingkai Li ,  Thomas Gehrke

发明人： Xiaolong Fang ,  Lifang Xu ,  Tingkai Li ,  Thomas Gehrke

IPC分类号： H01L33/48

CPC分类号： H01L33/32 ,  H01L21/78 ,  H01L22/10 ,  H01L22/32 ,  H01L22/34 ,  H01L23/544 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/48 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

公开(公告)号：US07723729B2

公开(公告)日：2010-05-25

申请号：US12036396

申请日：2008-02-25

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L31/0312 ,  H01L29/20 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/045 ,  H01L29/0673

摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

公开(公告)号：US20080164569A1

公开(公告)日：2008-07-10

申请号：US11582275

申请日：2006-10-16

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L29/00

CPC分类号： H01L27/15 ,  H01L33/0004 ,  H01L33/343

摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

摘要翻译： 一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。 根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

公开(公告)号：US07358160B2

公开(公告)日：2008-04-15

申请号：US11481437

申请日：2006-07-06

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L21/36

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/7624

摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where X≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或Si X N Y ，其中 X <= 3 AND Y <= 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。