公开(公告)号：US5433651A

公开(公告)日：1995-07-18

申请号：US173294

申请日：1993-12-22

申请人： Naftali E. Lustig ,  Katherine L. Saenger ,  Ho-Ming Tong

发明人： Naftali E. Lustig ,  Katherine L. Saenger ,  Ho-Ming Tong

IPC分类号： G01N21/55 ,  B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  B24D7/12 ,  G01B11/06 ,  H01L21/304 ,  H01L21/66 ,  B24B49/00

CPC分类号： B24B37/013 ,  B24D7/12 ,  G01B11/0683

摘要： An in-situ chemical-mechanical polishing process monitor apparatus for monitoring a polishing process during polishing of a workpiece in a polishing machine, the polishing machine having a rotatable polishing table provided with a polishing slurry, is disclosed. The apparatus comprises a window embedded within the polishing table, whereby the window traverses a viewing path during polishing and further enables in-situ viewing of a polishing surface of the workpiece from an underside of the polishing table during polishing as the window traverses a detection region along the viewing path. A reflectance measurement means is coupled to the window on the underside of the polishing table for measuring a reflectance, the reflectance measurement means providing a reflectance signal representative of an in-situ reflectance, wherein a prescribed change in the in-situ reflectance corresponds to a prescribed condition of the polishing process.

摘要翻译： 公开了一种用于在研磨机中抛光工件时的抛光工艺的原位化学机械抛光过程监控装置，抛光机具有一个设置有抛光浆料的旋转抛光台。 该装置包括嵌入在抛光台内的窗口，由此窗口在抛光期间横穿观察路径，并且还可以在抛光期间从抛光台的下侧在抛光过程中从工件的下侧观察抛光表面，因为窗口穿过检测区域 沿着观察路径。 反射率测量装置耦合到抛光台下侧的窗口以测量反射率，反射率测量装置提供表示原位反射率的反射信号，其中原位反射率的规定变化对应于 抛光过程的规定条件。

公开(公告)号：US20110086473A1

公开(公告)日：2011-04-14

申请号：US12972771

申请日：2010-12-20

申请人： Haizhou Yin ,  John A. Ott ,  Katherine L. Saenger ,  Chun-Yung Sung

发明人： Haizhou Yin ,  John A. Ott ,  Katherine L. Saenger ,  Chun-Yung Sung

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/02694 ,  H01L21/02532 ,  H01L21/76264 ,  Y10S438/973

摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.

摘要翻译： 本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。 具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片 （011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

公开(公告)号：US07785939B2

公开(公告)日：2010-08-31

申请号：US11566579

申请日：2006-12-04

申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Katherine L. Saenger

发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Katherine L. Saenger

IPC分类号： H01L21/00

CPC分类号： H01L21/02667 ,  H01L21/02609 ,  H01L21/2022 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

摘要： A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

摘要翻译： 提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。 还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

公开(公告)号：US20100044758A1

公开(公告)日：2010-02-25

申请号：US12197459

申请日：2008-08-25

申请人： GUY M. COHEN ,  Katherine L. Saenger

发明人： GUY M. COHEN ,  Katherine L. Saenger

IPC分类号： H01L29/04 ,  H01L21/84 ,  G06F19/00

CPC分类号： H01L27/0924 ,  H01L21/34 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different from each other. A volume of material is formed that extends through the first layer from the second layer up to the surface of the first layer. The material has a crystalline orientation that substantially matches the orientation of the second layer. Areas of the surface of the first layer that are outside of the region are selectively etched to create a first plurality of fins and areas inside the region to create a second plurality of fins. The etching leaves the first and second pluralities of fins parallel to each other with different surface crystal orientations.

摘要翻译： 制造具有至少一个p-FinFET器件和至少一个彼此平行的n-FinFET器件的集成电路。 具有第一晶体取向的第一硅层被结合到具有第二晶体取向的第二硅层上。 第一和第二取向彼此不同。 形成一定体积的材料，其从第二层延伸穿过第一层直到第一层的表面。 该材料具有基本上与第二层的取向一致的晶体取向。 选择性地蚀刻在区域外部的第一层的表面的区域，以在该区域内产生第一多个散热片和区域，以产生第二多个散热片。 蚀刻使得第一和第二多个翅片彼此平行但具有不同的表面晶体取向。

公开(公告)号：US20080248626A1

公开(公告)日：2008-10-09

申请号：US11697102

申请日：2007-04-05

申请人： Yaocheng Liu ,  Zhijiong Luo ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Rajasekhar Venigalla ,  Haizhou Yin

发明人： Yaocheng Liu ,  Zhijiong Luo ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Rajasekhar Venigalla ,  Haizhou Yin

IPC分类号： H01L21/762

CPC分类号： H01L21/26506 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/76224

摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.

摘要翻译： 通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB） 顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。 用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。 在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。 由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

公开(公告)号：US20080142894A1

公开(公告)日：2008-06-19

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L27/088 ,  H01L29/423

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20080108184A1

公开(公告)日：2008-05-08

申请号：US11566579

申请日：2006-12-04

申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Katherine L. Saenger

发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Katherine L. Saenger

IPC分类号： H01L21/84

CPC分类号： H01L21/02667 ,  H01L21/02609 ,  H01L21/2022 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

摘要： A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

摘要翻译： 提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。 还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US5633781A

公开(公告)日：1997-05-27

申请号：US577168

申请日：1995-12-22

申请人： Katherine L. Saenger ,  David E. Kotecki

发明人： Katherine L. Saenger ,  David E. Kotecki

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01K1/16

CPC分类号： H01L27/1085 ,  H01L27/10852 ,  H01L28/40

摘要： A capacitor structure is provided, with a first conductor on top of a substrate having at least one layer of dielectric material thereon; a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein; a second conductor, in electrical contact with the first conductor, formed on the sidewalls of the first opening; a non-conductive sidewall spacer formed in the first opening and contacting the second conductor, the non-conductive sidewall spacer having a second opening formed therein; and a third conductor formed in the second opening.

摘要翻译： 提供一种电容器结构，其中第一导体位于衬底的顶部，其上具有至少一层电介质材料; 在第一导体顶部并基本上与第一导体对准的第一非导体，第一导体和第一非导体具有形成在其中的第一开口; 与第一导体电接触的第二导体，形成在第一开口的侧壁上; 形成在所述第一开口中并接触所述第二导体的非导电侧壁间隔物，所述非导电侧壁间隔件具有形成在其中的第二开口; 以及形成在第二开口中的第三导体。

公开(公告)号：US08785911B2

公开(公告)日：2014-07-22

申请号：US13167570

申请日：2011-06-23

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

IPC分类号： H01L21/336

CPC分类号： H01L29/7781 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/1075 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055

摘要： Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

摘要翻译： 提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。