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202 条记录 (耗时 0.035 秒)

    High density integral test probe
    72.
    发明授权
    High density integral test probe 失效
    高密度积分测试探头

    公开(公告)号：US07276919B1

    公开(公告)日：2007-10-02

    申请号：US08756830

    申请日：1996-11-20

    申请人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George Frederick Walker

    发明人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George Frederick Walker

    IPC分类号： G01R31/06

    CPC分类号： G01R1/07314 ,  G01R1/06761 ,  G01R1/0735

    摘要： A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.

    摘要翻译： 描述了高密度集成测试探针和制造方法。 将一组电线球焊接到扇形外壳的表面上的接触位置。 电线被剪断，留下一个短截线，其末端被砧平坦化。 在平坦化具有一组孔的材料的片材之前，布置成使一组短截线对准，以便将短截线组放置在短截线上。 该材料片支撑放大的尖端。 具有短截线的基底形成探针，该探针移动成与诸如滴液或包装基底的工件上的接触位置接合。

    High density integrated circuit apparatus, test probe and methods of use thereof
    74.
    发明申请
    High density integrated circuit apparatus, test probe and methods of use thereof 审中-公开
    高密度集成电路设备，测试探针及其使用方法

    公开(公告)号：US20050062492A1

    公开(公告)日：2005-03-24

    申请号：US10408200

    申请日：2003-04-04

    申请人： Brian Beaman ,  Keith Fogel ,  Paul Lauro ,  Maurice Norcott ,  Da-Yuan Shih ,  George Walker

    发明人： Brian Beaman ,  Keith Fogel ,  Paul Lauro ,  Maurice Norcott ,  Da-Yuan Shih ,  George Walker

    IPC分类号： G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H05K1/00 ,  G01R31/02 ,  G01R31/26

    CPC分类号： G01R1/0735 ,  G01R1/06744 ,  G01R1/0675 ,  G01R1/07307 ,  G01R1/07378 ,  G01R3/00

    摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

    摘要翻译： 本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为离散芯片的装置。 测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。 使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。 电线被连接到空间变压器表面上的接触焊盘阵列。 空间变压器由多层集成电路芯片封装基板形成。 电线与接触位置阵列一样密集。 围绕着向外突出的线的阵列设置模具。 液体弹性体设置在模具中以填充电线之间的空间。 弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上， 其中细长导体被接合。 这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。 或者，插入器电连接器可以设置在第一和第二空间变压器之间。

    Use of tapered head pin design to improve the stress distribution in the braze joint
    78.
    发明授权
    Use of tapered head pin design to improve the stress distribution in the braze joint 失效
    采用锥形头针设计，提高钎焊接头的应力分布

    公开(公告)号：US4970570A

    公开(公告)日：1990-11-13

    申请号：US423613

    申请日：1989-10-16

    申请人： Birendra N. Agarwala ,  Paul H. Palmateer ,  Da-Yuan Shih

    发明人： Birendra N. Agarwala ,  Paul H. Palmateer ,  Da-Yuan Shih

    IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/34

    CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K3/3426

    摘要： The present invention teaches a structure for reducing the stresses created on a substrate and on the bonding surface at which a connector is attached. The connector has a tapered or beveled head thereby tapering the stress away from the edges of the bonding surface and therefore away from the high stress areas of the substrate, preventing cracking and delamination problems that might otherwise result. The tapered-head geometry also allows greater flexibility in manufacturing the connectors particularly when fabricating pins using a cold-heading process in that a quarter shank diameter:pin head diameter ratio can be obtained.

    摘要翻译： 本发明教导了一种用于减少在基板上以及在连接器所在的接合表面上产生的应力的结构。 连接器具有锥形或倾斜的头部，从而使应力使结合表面的边缘远离并且因此远离基板的高应力区域，从而防止否则可能导致的开裂和分层问题。 锥形头几何形状还允许制造连接器时的更大的灵活性，特别是当使用冷镦工艺制造销时，因为可以获得四分之一直径：销头直径比。