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    Anchored damascene structures
    71.
    发明授权
    Anchored damascene structures 有权
    锚定镶嵌结构

    公开(公告)号：US08368220B2

    公开(公告)日：2013-02-05

    申请号：US11252498

    申请日：2005-10-18

    申请人： David Lu ,  Horng-Huei Tseng ,  Syun-Ming Jang

    发明人： David Lu ,  Horng-Huei Tseng ,  Syun-Ming Jang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps.

    摘要翻译： 埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤。

    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS
    72.
    发明申请
    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS 有权
    GAP填充方法双重DAMASCENE过程

    公开(公告)号：US20120319278A1

    公开(公告)日：2012-12-20

    申请号：US13161701

    申请日：2011-06-16

    申请人： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    发明人： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

    摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。

    BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE
    78.
    发明申请
    BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE 有权
    半导体器件中的瓶颈记录

    公开(公告)号：US20110049567A1

    公开(公告)日：2011-03-03

    申请号：US12841763

    申请日：2010-07-22

    申请人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

    发明人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

    摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

    摘要翻译： 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹部进行无偏压蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中形成半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

    Method for forming a strained channel in a semiconductor device
    79.
    发明授权
    Method for forming a strained channel in a semiconductor device 有权
    在半导体器件中形成应变通道的方法

    公开(公告)号：US07754571B2

    公开(公告)日：2010-07-13

    申请号：US11592204

    申请日：2006-11-03

    申请人： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

    发明人： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636

    摘要： A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

    摘要翻译： 提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，该晶体管包括在半导体衬底上暴露有栅电极的栅极叠层，在栅极叠层的相对侧上的衬底中的一对源极/漏极区域 以及在栅极堆叠的相对的侧壁上的一对隔板。 形成钝化层以覆盖晶体管的栅电极和间隔物。 形成钝化层以覆盖栅电极和间隔物。 在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。 用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

    Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
    80.
    发明授权
    Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method 失效
    半导体器件具有在第一级上形成的第二级金属化，对第一级具有最小的损伤和方法

    公开(公告)号：US07732326B2

    公开(公告)日：2010-06-08

    申请号：US11497595

    申请日：2006-08-02

    申请人： Tien-I Bao ,  Syun-Ming Jang

    发明人： Tien-I Bao ,  Syun-Ming Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/31116 ,  H01L21/76807 ,  H01L21/76834 ,  H01L2221/1089

    摘要： A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.

    摘要翻译： 一种用于处理半导体结构的方法包括以下步骤：用薄的阻挡层覆盖限定金属化层的半导体结构的顶表面，在薄的停止层上形成电介质层，其中介电层限定至少一个区域， 暴露薄的止挡层，并且使用基本上不含氧的蚀刻剂气体去除暴露的薄止挡层以暴露金属化层的顶表面，使得金属化层基本上没有损坏。