公开(公告)号：US20170365715A1

公开(公告)日：2017-12-21

申请号：US15674266

申请日：2017-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L29/7847 ,  H01L21/31155 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

公开(公告)号：US09780192B2

公开(公告)日：2017-10-03

申请号：US15093881

申请日：2016-04-08

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/32

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

公开(公告)号：US20170133361A1

公开(公告)日：2017-05-11

申请号：US15414164

申请日：2017-01-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Sunitha Venkataraman ,  David L. Catlett, JR.

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/08 ,  H01L27/092 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/0814 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

公开(公告)号：US09190277B2

公开(公告)日：2015-11-17

申请号：US13709961

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/24 ,  H01L21/40 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0738 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/0629 ,  H01L28/20

Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.

Abstract translation: 包含PMOS晶体管的集成电路可以通过在p沟道源极漏极（PSD）注入步骤中以与有效沟道长度控制，退火PSD注入一致的剂量注入硼并随后同时将硼注入多晶硅电阻器中而形成， 使用也暴露PMOS晶体管的注入掩模的零电阻温度系数，接着是毫秒退火。

公开(公告)号：US20150187659A1

公开(公告)日：2015-07-02

申请号：US14575490

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/66545 ,  H01L29/6659

Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.

Abstract translation: 在高k电介质下形成具有高质量栅极电介质的替代金属栅极晶体管。 在至少850℃的温度下在衬底上形成高质量的栅极电介质。在高质量栅极电介质上形成牺牲栅极电介质，并且在牺牲栅极电介质上形成多晶硅替代栅极。 去除多晶硅替代栅极留下栅极沟槽。 从栅极的底部去除牺牲栅极电介质。 高k电介质沉积到栅极沟槽中。 金属栅极材料沉积在高k电介质上。

公开(公告)号：US08962406B2

公开(公告)日：2015-02-24

申请号：US14497524

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.

公开(公告)号：US08927385B2

公开(公告)日：2015-01-06

申请号：US13716424

申请日：2012-12-17

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Deborah J. Riley ,  Amitabh Jain

IPC: H01L21/20 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract translation: 可以通过去除电阻器区域中的多晶硅层的顶表面的部分来形成具有替换栅极MOS晶体管和多晶硅电阻器的集成电路。 随后形成的栅极蚀刻硬掩模包括MOS牺牲栅极上的MOS硬掩模段和电阻体上的电阻器硬掩模段。 电阻体比MOS牺牲栅极薄。 在栅极替换处理序列期间，去除MOS硬掩模段，暴露MOS牺牲栅极，同时电阻器硬掩模段的至少一部分保留在电阻体上。 当不更换电阻体时，MOS牺牲栅极被替换栅极替代。

公开(公告)号：US08865557B1

公开(公告)日：2014-10-21

申请号：US14457209

申请日：2014-08-12

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/336 ,  H01L49/02 ,  H01L21/265

CPC classification number: H01L28/20 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7847 ,  H01L29/94

Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Abstract translation: 在本发明的实施例中，公开了形成NMOS（n型金属氧化物半导体）晶体管的方法。 双掩模图案用于离子注入NMOS晶体管的源极/漏极区域。 第一个掩模允许第一剂量的As（砷），P（磷）和N（氮）离子注入。 在这些剂量被离子注入之后，进行高温（900-1050℃）尖峰退火以激活形成的源/排水沟。 第二掩模允许在源极/漏极区域中注入第二剂量的磷。 磷的第二剂量通常高于第一剂量的磷。 磷的第二剂量降低了Rsd（源区和漏区的电阻）和掺杂n型多晶硅块。

公开(公告)号：US08835270B2

公开(公告)日：2014-09-16

申请号：US13689433

申请日：2012-11-29

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/336 ,  H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L28/20 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7847 ,  H01L29/94

Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Abstract translation: 在本发明的实施例中，公开了形成NMOS（n型金属氧化物半导体）晶体管的方法。 双掩模图案用于离子注入NMOS晶体管的源极/漏极区域。 第一个掩模允许第一剂量的As（砷），P（磷）和N（氮）离子注入。 在这些剂量被离子注入之后，进行高温（900-1050℃）尖峰退火以激活形成的源/排水沟。 第二掩模允许在源极/漏极区域中注入第二剂量的磷。 磷的第二剂量通常高于第一剂量的磷。 磷的第二剂量降低了Rsd（源区和漏区的电阻）和掺杂n型多晶硅块。

公开(公告)号：US20140167182A1

公开(公告)日：2014-06-19

申请号：US13716424

申请日：2012-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Deborah J. Riley ,  Amitabh Jain

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract translation: 可以通过去除电阻器区域中的多晶硅层的顶表面的部分来形成具有替换栅极MOS晶体管和多晶硅电阻器的集成电路。 随后形成的栅极蚀刻硬掩模包括MOS牺牲栅极上的MOS硬掩模段和电阻体上的电阻器硬掩模段。 电阻体比MOS牺牲栅极薄。 在栅极替换处理序列期间，去除MOS硬掩模段，暴露MOS牺牲栅极，同时电阻器硬掩模段的至少一部分保留在电阻体上。 当不更换电阻体时，MOS牺牲栅极被替换栅极替代。