公开(公告)号：US20240379781A1

公开(公告)日：2024-11-14

申请号：US18780151

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Hao Lu ,  Li-Li Su ,  Chien-I Kuo ,  Yee-Chia Yeo ,  Wei-Yang Lee ,  Yu-Xuan Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

公开(公告)号：US20240379616A1

公开(公告)日：2024-11-14

申请号：US18783770

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Cheng-I Chu ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/66

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

公开(公告)号：US20240379454A1

公开(公告)日：2024-11-14

申请号：US18779272

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US20240379407A1

公开(公告)日：2024-11-14

申请号：US18783544

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yen Chen ,  Li-Ting Wang ,  Wan-Chen Hsieh ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/764 ,  H01L21/768

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

公开(公告)号：US12132118B2

公开(公告)日：2024-10-29

申请号：US17231183

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/66742

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

公开(公告)号：US12112977B2

公开(公告)日：2024-10-08

申请号：US18190297

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Meng-Han Chou

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/785

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

公开(公告)号：US12080759B2

公开(公告)日：2024-09-03

申请号：US17530026

申请日：2021-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Wei-Jen Lai ,  Chien-I Kuo ,  Wei-Yuan Lu ,  Chia-Pin Lin ,  Yee-Chia Yeo

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

公开(公告)号：US12074026B2

公开(公告)日：2024-08-27

申请号：US17749038

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Shian Chen ,  Li-Ting Wang ,  Yee-Chia Yeo

IPC: H01L21/027

CPC classification number: H01L21/0272 ,  H01L21/0275

Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.

公开(公告)号：US12068322B2

公开(公告)日：2024-08-20

申请号：US17161978

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Tang ,  Hung-Tai Chang ,  Ming-Hua Yu ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823814 ,  H01L29/7848

Abstract: An embodiment includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, an outer surface of the epitaxial first source/drain region having more than eight facets in a first plane, the first plane being orthogonal to a top surface of the substrate.

公开(公告)号：US20240274606A1

公开(公告)日：2024-08-15

申请号：US18646277

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.