公开(公告)号：US06713359B1

公开(公告)日：2004-03-30

申请号：US09564191

申请日：2000-05-04

申请人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

发明人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/28052 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665

摘要： SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.

摘要翻译： SiGe或SiC膜选择性地在源极/漏极区域上生长，随后选择性地生长硅。 通过使C或Ge浓度高于预定水平，可以在生长硅膜时生长具有高位错密度的单晶膜或多晶膜。 源极/漏极区域中的每一个上的硅层不是单晶的，即使单晶也具有高密度的位错。 因此，其上形成的硅膜是具有高位错密度的单晶硅膜或多晶硅膜的形式。 可以通过离子注入来抑制在掺杂步骤中产生的离子的沟道引起的深度区域的杂质扩散。

公开(公告)号：US06600189B1

公开(公告)日：2003-07-29

申请号：US09598379

申请日：2000-06-21

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

IPC分类号： H01L27108

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/909

摘要： A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

摘要翻译： 半导体器件包括在其表面上具有沟槽的半导体衬底和嵌入沟槽内部的嵌入构件。 虽然当垂直于沟槽深度方向的第一平面切割沟槽的部分被定义为第一部分，并且当垂直于沟槽深度方向的第二平面切割沟槽的部分时 并且比所述第一平面更靠近所述沟槽的底部被限定为第二部分，所述第一部分的面积小于所述第二部分的面积，并且所述第一部分的最小曲率半径小于所述第一部分的最小半径 第二部分的曲率。 结果，可以减小进入沟槽底部的电场的浓度。

公开(公告)号：US06570217B1

公开(公告)日：2003-05-27

申请号：US09296669

申请日：1999-04-22

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

IPC分类号： H01L2926

CPC分类号： H01L29/66583 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/78639

摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

公开(公告)号：US06313047B2

公开(公告)日：2001-11-06

申请号：US09811451

申请日：2001-03-20

申请人： Kazuhide Hasebe ,  Yuichiro Morozumi ,  Dong-Kyun Choi ,  Takuya Sugawara ,  Seiji Inumiya ,  Yoshitaka Tsunashima

发明人： Kazuhide Hasebe ,  Yuichiro Morozumi ,  Dong-Kyun Choi ,  Takuya Sugawara ,  Seiji Inumiya ,  Yoshitaka Tsunashima

IPC分类号： H01L2131

CPC分类号： H01L21/02183 ,  C23C16/0272 ,  C23C16/405 ,  H01L21/02271 ,  H01L21/31604

摘要： Disclosed is an MOCVD method of forming a tantalum oxide film. First, water vapor used as an oxidizing agent is supplied into a process container to cause moisture to be adsorbed on a surface of each semiconductor wafer. Then, PET gas used as a raw material gas is supplied into the process container and is caused to react with the moisture on the wafer at a process temperature of 200° C., thereby forming an interface layer of tantalum oxide. Then, PET gas and oxygen gas are supplied into the process container at the same time, and are caused to react with each other at a process temperature of 410° C., thereby forming a main layer of tantalum oxide on the interface layer.

摘要翻译： 公开了一种形成氧化钽膜的MOCVD方法。 首先，将作为氧化剂使用的水蒸气供给到处理容器中，使得水分吸附在各半导体晶片的表面上。 然后，将作为原料气体使用的PET气体供给到处理容器中，并在200℃的处理温度下与晶片上的水分反应，由此形成氧化钽界面层。 然后，将PET气体和氧气同时供给到处理容器中，并在410℃的处理温度下彼此反应，从而在界面层上形成氧化钽的主层。

公开(公告)号：US06232641B1

公开(公告)日：2001-05-15

申请号：US09321846

申请日：1999-05-28

申请人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Tomohiro Saito

发明人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Tomohiro Saito

IPC分类号： H01L31119

CPC分类号： H01L29/66628 ,  H01L29/66545

摘要： A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate. A second gate-side-wall insulating film is formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film. The portion formed on the bottom surface exists in an inner bottom surface portion of the bottom surface of the first gate-side-wall insulating film adjacent to the gate electrode. The elevated source film and the elevated drain film are free from any facet in portions made contact with the first gate-side-wall insulating film.

摘要翻译： 形成具有升高的源极和漏极结构的MOS晶体管的半导体器件被布置成具有通过绝缘膜形成在硅衬底的表面上的栅电极。 在硅的表面上的源极区域和漏极区域上形成有在硅衬底的表面上导电且升高的至少一层由金属硅化物膜构成的表面部分的升高的源极膜和升高的漏极膜 基质。 因此，形成具有使源极区域和漏极区域的表面在硅衬底的表面上升高的结构的MOS晶体管。 第一栅极侧壁绝缘膜形成在MOS晶体管的栅电极的侧壁上，并且具有与硅衬底的表面分开形成的底表面。 在第一栅极侧壁绝缘膜和栅电极之间以及第一栅极侧壁绝缘膜的底面上形成第二栅极侧壁绝缘膜。 形成在底表面上的部分存在于与栅电极相邻的第一栅极侧壁绝缘膜的底表面的内底表面部分中。 升高的源极膜和升高的漏极膜在与第一栅极侧壁绝缘膜接触的部分中没有任何刻面。

公开(公告)号：US5173440A

公开(公告)日：1992-12-22

申请号：US517331

申请日：1990-05-01

申请人： Yoshitaka Tsunashima ,  Kenji Todori ,  Kikuo Yamabe

发明人： Yoshitaka Tsunashima ,  Kenji Todori ,  Kikuo Yamabe

IPC分类号： H01L21/225 ,  H01L21/334 ,  H01L21/336

CPC分类号： H01L29/66181 ,  H01L21/2255 ,  H01L29/66575 ,  Y10S148/014

摘要： In fabricating a semiconductor device, when impurities are diffused from a silicon oxide layer containing the impurities to a semiconductor layer, a diffusion atmosphere is controlled so as to oxidize or reduce a specified impurity to thereby control the diffusion coefficient of the impurities in the silicon oxide layer. Thus, it is possible to form a diffusion layer having a desired impurity profile under a good control.

摘要翻译： 在制造半导体器件时，当杂质从包含杂质的氧化硅层扩散到半导体层时，控制扩散气氛以氧化或减少特定杂质，从而控制氧化硅中杂质的扩散系数 层。 因此，可以在良好的控制下形成具有所需杂质分布的扩散层。

公开(公告)号：US5069244A

公开(公告)日：1991-12-03

申请号：US635655

申请日：1990-12-28

申请人： Shinji Miyazaki ,  Yoshitaka Tsunashima

发明人： Shinji Miyazaki ,  Yoshitaka Tsunashima

IPC分类号： B01J7/00 ,  C23C16/44 ,  C23C16/448 ,  C30B25/14 ,  H01L21/205

CPC分类号： C23C16/448 ,  C30B25/14 ,  Y10T137/3127 ,  Y10T137/4259

摘要： A liquid source container device is used for a liquid gas source for a semiconductor manufacturing device. This container device includes a main body for containing a source liquid, to which a gas supply line for transferring the source liquid, and a source liquid delivery line for delivering the liquid are connected. The gas supply line has first and second gas supply valves provided thereon, and the liquid delivery line has first and second liquid delivery valves also provided thereon. A section of the gas supply line which is located between the first and second gas supply valves and a section of the liquid delivery line which is located between the first and second delivery valves are connected with each other by means of a purge line which has a purge valve provided thereon. By operating the purge line, the purge valve, and the four valves, the efficiency of purge-drying procedures carried out before and after transferring the source liquid, is improved, and therefore the container device, as well as the semiconductor manufacturing device can be prevented from being contaminated.

公开(公告)号：US08796757B2

公开(公告)日：2014-08-05

申请号：US13052177

申请日：2011-03-21

申请人： Tetsuya Kai ,  Yoshio Ozawa ,  Ryota Fujitsuka ,  Yoshitaka Tsunashima

发明人： Tetsuya Kai ,  Yoshio Ozawa ,  Ryota Fujitsuka ,  Yoshitaka Tsunashima

IPC分类号： H01L29/792

CPC分类号： H01L29/66666 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.

摘要翻译： 根据一个实施例，具有每个由垂直晶体管组成的存储单元的半导体存储器件包括在硅衬底上形成为柱状的硅层，其中隧道绝缘膜，电荷存储层， 并且形成块状绝缘膜以包围硅层的侧壁表面，以及堆叠结构部分，其形成为围绕栅极绝缘膜部分的侧壁表面，并且其中多个层间绝缘膜和多个控制栅电极 层交替堆叠。 硅层，栅极绝缘膜部分和控制栅极电极层构成垂直晶体管。 电荷存储层的陷阱水平低于垂直晶体管之间的面对控制栅极电极层的区域。

公开(公告)号：US07947610B2

公开(公告)日：2011-05-24

申请号：US12471830

申请日：2009-05-26

申请人： Yoshitaka Tsunashima ,  Seiji Inumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Inumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US07501335B2

公开(公告)日：2009-03-10

申请号：US10999937

申请日：2004-12-01

申请人： Katsuyuki Sekine ,  Yoshitaka Tsunashima ,  Seiji Inumiya ,  Akio Kaneko ,  Motoyuki Sato ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Yoshitaka Tsunashima ,  Seiji Inumiya ,  Akio Kaneko ,  Motoyuki Sato ,  Kazuhiro Eguchi

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/469

CPC分类号： H01L21/02321 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/022 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31645 ,  H01L29/518

摘要： A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using ND3 gas.

摘要翻译： 本文公开的半导体器件的制造方法包括：在基板上形成含有金属的硅酸盐膜; 并通过使用ND3气体将氮和氘引入硅酸盐膜。