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    BUS ARCHITECTURE WITH TRANSACTION CREDIT SYSTEM
    74.
    发明申请
    BUS ARCHITECTURE WITH TRANSACTION CREDIT SYSTEM 有权

    公开(公告)号：US20250045230A1

    公开(公告)日：2025-02-06

    申请号：US18814700

    申请日：2024-08-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： David M. Thompson ,  Timothy D. Anderson ,  Joseph R.M. Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

    IPC: G06F13/40 ,  G06F13/364 ,  G06F13/42 ,  H04L47/10 ,  H04L47/215

    Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

    VECTOR REVERSE
    77.
    发明公开
    VECTOR REVERSE 审中-公开

    公开(公告)号：US20240201991A1

    公开(公告)日：2024-06-20

    申请号：US18404238

    申请日：2024-01-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. Anderson ,  Duc Bui

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3013

    Abstract: Processors and methods reverse source data in response to a vector reverse instruction. In an implementation, a processor comprises an instruction fetch unit; and a datapath that includes a register file that includes a source register and a destination register; and a set of functional units. The instruction fetch unit receives a vector reverse instruction that specifies a single vector reverse operation to be executed in a single operation. The vector reverse instruction also specifies a first functional unit from among a set of functional units, and based on the vector reverse instruction, the first functional unit receives the first vector from a source register; reverses an order of a set of elements of a first vector stored in the source register to produce a second vector; and causes the second vector to be stored in a destination register.

    NESTED LOOP CONTROL
    78.
    发明公开
    NESTED LOOP CONTROL 审中-公开

    公开(公告)号：US20240086193A1

    公开(公告)日：2024-03-14

    申请号：US18507222

    申请日：2023-11-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

    IPC: G06F9/30

    CPC classification number: G06F9/30065 ,  G06F9/3013

    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

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