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    Semiconductor memory device
    73.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06940739B2

    公开(公告)日：2005-09-06

    申请号：US10307954

    申请日：2002-12-03

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    摘要翻译： 存储器结构/电路具有至少两个相互连接的存储单元阵列。 两个或多个存储单元阵列的位线通过分层开关连接。 通过使用层次结构开关选择一个阵列而不选择其他阵列，其中一个阵列的存储单元可以比其他阵列更快地读出。 因此，如果存储在更快的访问存储器阵列中，则可以更快地选择性地读出更高频率读取的数据。 如果快速访问存储单元阵列中的数据包含另一阵列中的数据副本，则可以将其用作高速缓冲存储器。 组合的标签阵列和数据阵列通过分层交换机连接组合连接到另一标签阵列和数据阵列，可以提供直接映射或设置关联的高速缓存存储器，也可以是完全关联的。 存储器件可用于具有CPU的半导体数据处理器，其中存储器件通过总线连接到CPU，其中CPU和存储器件均形成在单个半导体衬底上。 存储器件也可以是片外器件。

    Semiconductor integrated circuit device
    74.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06930504B2

    公开(公告)日：2005-08-16

    申请号：US10869934

    申请日：2004-06-18

    申请人： Koichiro Ishibashi

    发明人： Koichiro Ishibashi

    IPC分类号： G01R31/26 ,  G11C29/02 ,  G11C29/26 ,  G11C29/50 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04

    CPC分类号： H01L22/34 ,  G11C29/02 ,  G11C29/26 ,  G11C29/50 ,  G11C2029/5006 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device is provided which includes a first circuit block connected to a first node and a second circuit block connected to a second node, wherein the second circuit block is provided on the same semiconductor chip as the first circuit block. A comparator is also provided to compare a first potential of the first node and a second potential of the second node. A first supply current in a quiescent state flows through the first node and the first circuit block, and a second supply current in a quiescent state flows through the second node and the second circuit block.

    摘要翻译： 提供了一种半导体集成电路器件，其包括连接到第一节点的第一电路块和连接到第二节点的第二电路块，其中第二电路块设置在与第一电路块相同的半导体芯片上。 还提供比较器以比较第一节点的第一电位和第二节点的第二电位。 处于静止状态的第一供电电流流过第一节点和第一电路块，并且处于静止状态的第二供电电流流经第二节点和第二电路块。

    Semiconductor memory device with memory cells operated by boosted voltage
    77.
    发明申请
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US20050024917A1

    公开(公告)日：2005-02-03

    申请号：US10926032

    申请日：2004-08-26

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/413 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C11/22

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is increased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor integrated circuit device
    78.
    发明申请
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US20050007183A1

    公开(公告)日：2005-01-13

    申请号：US10911664

    申请日：2004-08-05

    申请人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Hiroyuki Mizuno

    发明人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Hiroyuki Mizuno

    IPC分类号： H03K3/01 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/00323 ,  H03K19/00384 ,  H03K19/018585

    摘要： A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.

    摘要翻译： 半导体集成电路器件包括执行预定处理的逻辑电路，向逻辑电路提供时钟信号的时钟发生器以及控制逻辑电路的操作速度的速度控制器。 在逻辑电路工作时，时钟发生器通过频率控制信号来改变时钟信号的频率，速度控制器根据时钟信号的变化来控制逻辑电路的工作速度。

    Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit
    80.
    发明授权
    Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit 有权
    包括衬底偏置控制器和限流电路的半导体集成电路器件

    公开(公告)号：US06778002B2

    公开(公告)日：2004-08-17

    申请号：US10207903

    申请日：2002-07-31

    申请人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Goichi Ono

    发明人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Goichi Ono

    IPC分类号： H03K301

    CPC分类号： G05F3/205

    摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

    摘要翻译： 在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度 用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。 还结合衬底偏置控制器提供限流电路，以防止由于偏置电压引起的电流溢出。