公开(公告)号：US5615165A

公开(公告)日：1997-03-25

申请号：US576564

申请日：1995-12-21

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

公开(公告)号：US5528547A

公开(公告)日：1996-06-18

申请号：US332391

申请日：1994-10-31

申请人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

发明人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/0483

摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

公开(公告)号：US5268867A

公开(公告)日：1993-12-07

申请号：US957001

申请日：1992-10-06

申请人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/10 ,  G11C16/06 ,  G11C16/20 ,  G11C16/26 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C16/20 ,  G11C16/26 ,  G11C5/147

摘要： The present invention provides a semiconductor memory device capable of reducing its current consumption, controlling the generation of noise, and increasing in access using a precharge voltage applied to a precharge circuit. In the semiconductor memory device, a precharge circuit is connected to a pair of data input/output lines, and includes a MOS transistor connected between one of the data input/output lines and a node of a precharge voltage and a MOS transistor connected between the other data input/output line and a node of the precharge voltage. The gates of the MOS transistors are supplied with control signals so that the MOS transistors are turned on when the data input/output lines are precharged. A MOS transistor is connected to the data input/output lines for equalizing them. The precharge voltage is set to half of a value obtained by subtracting the threshold voltage of the MOS transistor from the power supply voltage.

摘要翻译： 本发明提供一种半导体存储器件，其能够降低其电流消耗，控制噪声的产生，并且使用施加到预充电电路的预充电电压来增加存取。 在半导体存储器件中，预充电电路连接到一对数据输入/输出线，并且包括连接在数据输入/输出线之一和预充电电压的节点之间的MOS晶体管和连接在 其他数据输入/输出线和预充电电压的节点。 MOS晶体管的栅极被提供控制信号，使得当数据输入/输出线被预充电时MOS晶体管导通。 MOS晶体管连接到数据输入/输出线，以使它们均衡。 预充电电压被设定为通过从电源电压减去MOS晶体管的阈值电压而获得的值的一半。

公开(公告)号：US5247480A

公开(公告)日：1993-09-21

申请号：US773723

申请日：1991-10-09

申请人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

发明人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

摘要： An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.

摘要翻译： 电可擦除可编程只读存储器具有存储单元块，每个存储单元块分别具有与位线相关联的NAND型单元单元。 每个单元单元具有浮置型存储单元晶体管的串联电路和设置在相应位线和存储单元晶体管的串联电路之间的选择晶体管。 向存储单元块共同地提供行解码器，用于产生提供给连接到选择晶体管的选择栅极控制线和单元单元中所选择的字线或线的“H”电平电压。 为每个存储单元块提供升压电路，用于使“H”电平电压增加到足以使单元晶体管导通的预选电位电平。 升压电路包括用于选择栅极控制线的第一升压部分和用于字线的第二部分。 第二部分响应于第一部分的输出电压而工作。

公开(公告)号：US4764693A

公开(公告)日：1988-08-16

申请号：US48813

申请日：1987-05-12

申请人： Yoshihisa Iwata

发明人： Yoshihisa Iwata

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/10 ,  G11C8/06 ,  G11C11/408 ,  H03K17/04 ,  H03K3/356 ,  H03K17/687 ,  H03K19/01

CPC分类号： G11C7/1057 ,  G11C7/065 ,  G11C7/1051 ,  G11C8/06

摘要： A sense circuit for use in a semiconductor memory senses an input signal by comparing the input signal with a reference voltage. The sense circuit comprises a sense amplifier having first and second nodes, and first and second transfer gates. The first transfer gate couples the input signal to the first node of the sense amplifier. The second transfer gate couples the reference voltage to the second node of the sense amplifier. A level-shift circuit is provided between the second node of the sense amplifier and the second transfer gate. In response to the voltage level of the input signal latched in the first node, the level-shift circuit shifts the level of the reference voltage latched in the second node of the sense amplifier to a lower level when the input signal is high in voltage level, and shifts it to a higher level when the input signal is low in voltage level.

摘要翻译： 用于半导体存储器的感测电路通过将输入信号与参考电压进行比较而感测输入信号。 感测电路包括具有第一和第二节点的读出放大器以及第一和第二传输门。 第一传输门将输入信号耦合到读出放大器的第一节点。 第二传输门将参考电压耦合到读出放大器的第二个节点。 在读出放大器的第二节点和第二传输门之间提供电平移位电路。 响应于在第一节点中锁存的输入信号的电压电平，当输入信号的电压电平高时，电平移位电路将读出放大器的第二节点中锁存的参考电压的电平移位到较低电平 ，并且当输入信号的电压电平低时，将其移动到更高的电平。

公开(公告)号：US08334551B2

公开(公告)日：2012-12-18

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US08203882B2

公开(公告)日：2012-06-19

申请号：US12718353

申请日：2010-03-05

申请人： Tomoo Hishida ,  Yoshihisa Iwata

发明人： Tomoo Hishida ,  Yoshihisa Iwata

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.

摘要翻译： 当在一个存储单元块中执行数据擦除操作时，将第一电压施加到从一个存储单元块中的m个源极线中选择的一个源极线。 在数据擦除操作开始之前等于源极线的电压的第二电压被施加到其它源极线。 然后，在施加第一电压的一定的时间延迟之后，将小于第一电压的第三电压施加到连接到所选择的源极线的源极侧选择晶体管的第三导电层。 然后，由于第一和第三电压之间的电位差，在第三栅极绝缘层附近产生空穴电流。 将第四电压施加到连接到要擦除的存储晶体管之一的第一导电层之一。 其他第一导电层进入浮置状态。

公开(公告)号：US08111538B2

公开(公告)日：2012-02-07

申请号：US12273874

申请日：2008-11-19

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Yoshihisa Iwata

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Yoshihisa Iwata

IPC分类号： G11C11/00

CPC分类号： G11C7/20 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C29/028 ,  G11C29/50 ,  G11C2013/0083 ,  G11C2029/1206 ,  G11C2029/5002 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.

摘要翻译： 半导体存储器件包括具有根据“0”数据/“1”数据被设置成低电阻状态/高电阻状态的多个存储器单元的存储单元阵列。 当电源接通时，切换“0”数据/“1”数据和低电阻状态/高电阻状态的分配。

公开(公告)号：US08107286B2

公开(公告)日：2012-01-31

申请号：US12684349

申请日：2010-01-08

申请人： Kiyotaro Itagaki ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

发明人： Kiyotaro Itagaki ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

IPC分类号： G11C16/26

CPC分类号： H01L27/11578 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from among the plurality of memory strings. During the read operation, the control circuit is configured to apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation.

摘要翻译： 非易失性半导体存储器件包括：具有多个存储器串的存储单元阵列，每个存储器串均具有串联连接的多个存储器单元; 以及控制电路，被配置为执行用于从所述多个存储器串中的所选择的存储器串中包括的存储单元读取数据的读取操作。 在读取操作期间，控制电路被配置为将第一电压施加到不经过读取操作的未选择的存储器串中的至少一个存储器单元的栅极，并施加低于第一电压的第二电压 到没有进行读取操作的未选择的存储器串中的另一个存储器单元的门。

公开(公告)号：US08084809B2

公开(公告)日：2011-12-27

申请号：US12408183

申请日：2009-03-20

申请人： Takashi Maeda ,  Yoshihisa Iwata

发明人： Takashi Maeda ,  Yoshihisa Iwata

IPC分类号： H01L29/792

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

摘要翻译： 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。